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| m68hc08 microcontrollers freescale.com mc68hc908ld64 data sheet mc68hc908ld64 rev. 3.0 07/2004
mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor 3 mc68hc908ld64 data sheet to provide the most up-to-date info rmation, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to veri fy you have the latest information available, refer to: http://www.freescale.com the following revision history table summarizes cha nges contained in this document. for your conven ience, the page number designators have been linked to the appropriate location. freescale and the freescale logo are trademarks of freescale semiconductor, inc. this product incorporates superflash? technology lic ensed from sst. ? freescale semiconductor, inc., 2004 revision history data sheet mc68hc908ld64 ? rev. 3.0 4 freescale semiconductor revision history date revision level description page number(s) july 2004 3 figure 13-2 . adc block diagram ? removed incorrect adiclk input to clock generator in block diagram. 179 18.7.1 osd control register (osdcr) ? corrected halfclk bit definitions. 278 18.7.2 osd status register (osdsr) ? corrected wrdy bit description. 278 18.7.3 osd data regi sters (osddrh:osddrl) ? corrected osdd[15:0] bits description. 279 18.8.3.5 frame control registers ? corrected osd_en bit location. 288 section 11. timer interface module (tim) ? corrected timer discrepancies throughout. 149 section 16. ddc12ab interface ? changed the prefix "d" to "ddc" in ddc12ab register na me abbreviations throughout. 235 mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor list of sections 5 data sheet ? mc68hc908ld64 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 31 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 3. random-a ccess memory (ram) . . . . . . . . . . 61 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . 63 section 5. configuration register (config) . . . . . . . . . 75 section 6. central processor unit (cpu) . . . . . . . . . . . . 77 section 7. oscillator (osc ) . . . . . . . . . . . . . . . . . . . . . . . 95 section 8. clock generator module (cgm) . . . . . . . . . . . 99 section 9. system integration module (sim) . . . . . . . . 113 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 137 section 11. timer interface module (tim) . . . . . . . . . . . 149 section 12. pulse width modulato r (pwm) . . . . . . . . . . 171 section 13. analog-to-digital converter (adc) . . . . . . 177 section 14. universal serial bu s module (usb) . . . . . . 187 section 15. multi-master iic in terface (mmiic) . . . . . . . 221 section 16. ddc12ab interface . . . . . . . . . . . . . . . . . . . 235 section 17. sync processo r . . . . . . . . . . . . . . . . . . . . . . 251 section 18. on-screen display (osd ) . . . . . . . . . . . . . . 271 section 19. input/output (i/o) port s . . . . . . . . . . . . . . . 293 section 20. external interrupt (irq ) . . . . . . . . . . . . . . . 315 section 21. keyboard interrupt module (kbi). . . . . . . . 321 section 22. computer operatin g properly (cop) . . . . 329 section 23. break module (brk) . . . . . . . . . . . . . . . . . . 335 section 24. electrical sp ecifications. . . . . . . . . . . . . . . 343 section 25. mechanical specificati ons . . . . . . . . . . . . . 357 section 26. ordering in formation . . . . . . . . . . . . . . . . . 359 list of sections data sheet mc68hc908ld64 ? rev. 3.0 6 list of sections freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor table of contents 7 data sheet ? mc68hc908ld64 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table of contents data sheet mc68hc908ld64 ? rev. 3.0 8 table of contents freescale semiconductor 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.4 flash control regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.1 osd flash even high byte write buffer (o sdehbuf) . . 67 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 flash block protect regi sters . . . . . . . . . . . . . . . . . . . . . . 72 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table of contents mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor table of contents 9 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .96 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 97 7.4.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 97 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 97 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 97 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 98 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.5 cgm i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.1 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 103 8.5.2 pll analog power pin (vdda) . . . . . . . . . . . . . . . . . . . . . 103 8.5.3 pll analog ground pin (vssa). . . . . . . . . . . . . . . . . . . . . 103 8.5.4 crystal output frequency signal (oscxclk). . . . . . . . . . 104 8.5.5 crystal reference frequency signal (oscrclk). . . . . . . 104 8.5.6 cgm base clock output (dclk1) . . . . . . . . . . . . . . . . . . . 104 8.5.7 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 104 table of contents data sheet mc68hc908ld64 ? rev. 3.0 10 table of contents freescale semiconductor 8.6 cgm i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 106 8.6.3 pll programming regi ster (ppg) . . . . . . . . . . . . . . . . . . . 108 8.6.4 h & v sync output control re gister (hvocr) . . . . . . . . . 110 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.9 cgm during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 112 section 9. system integration module (sim) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 117 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.2 clock start-up from po r . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 117 9.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 119 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 9.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 121 9.4.2.3 low-voltage inhibit re set . . . . . . . . . . . . . . . . . . . . . . .121 9.4.2.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.4.2.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .122 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 122 9.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 122 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 123 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table of contents mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor table of contents 11 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 129 9.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 129 9.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 130 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 134 9.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 135 9.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 136 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 section 11. timer interface module (tim) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table of contents data sheet mc68hc908ld64 ? rev. 3.0 12 table of contents freescale semiconductor 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 154 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .155 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 155 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 156 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 157 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 161 11.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 163 11.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 164 11.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 165 11.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 168 section 12. pulse width modulator (pwm) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 12.4 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.4.1 pwm data registers 0 to 7 (0 pwm?7pwm). . . . . . . . . . . 173 12.4.2 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . . 174 table of contents mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor table of contents 13 section 13. analog-to-dig ital converter (adc) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 13.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 13.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7.1 adc analog power pin (vdda). . . . . . . . . . . . . . . . . . . . . 182 13.7.2 adc analog ground pin (vssa) . . . . . . . . . . . . . . . . . . . .182 13.7.3 adc voltage reference high pin (v rh) . . . . . . . . . . . . . . 182 13.7.4 adc voltage reference low pin ( vrl). . . . . . . . . . . . . . . 182 13.7.5 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .183 13.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 185 section 14. universal se rial bus module (usb) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 14.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 14.5 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 table of contents data sheet mc68hc908ld64 ? rev. 3.0 14 table of contents freescale semiconductor 14.6 hub function i/o r egisters . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.6.1 usb hub root port control r egister (hrpcr) . . . . . . . . . 194 14.6.2 usb hub downstream port control registers (hdp1cr?hdp4cr) . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.6.3 usb sie timing interr upt register (sietir) . . . . . . . . . . . 198 14.6.4 usb sie timing stat us register (sietsr) . . . . . . . . . . . . 200 14.6.5 usb hub address regi ster (haddr) . . . . . . . . . . . . . . . . 202 14.6.6 usb hub interrupt r egister 0 (hir0) . . . . . . . . . . . . . . . . . 203 14.6.7 usb hub control regi ster 0 (hcr0) . . . . . . . . . . . . . . . . . 205 14.6.8 usb hub endpoint 1 control and data register (hcdr) . 206 14.6.9 usb hub status regist er (hsr) . . . . . . . . . . . . . . . . . . . . 208 14.6.10 usb hub endpoint 0 data r egisters (he0d0?he0d7). . . 209 14.7 embedded device function i/o registers . . . . . . . . . . . . . . . 209 14.7.1 usb embedded devi ce address register (daddr). . . . . 210 14.7.2 usb embedded device interrupt register 0 (dir0) . . . . . 210 14.7.3 usb embedded device interrupt register 1 (dir1) . . . . . 212 14.7.4 usb embedded device control register 0 (dcr0) . . . . . 213 14.7.5 usb embedded device control register 1 (dcr1) . . . . . 215 14.7.6 usb embedded device control register 2 (dcr2) . . . . . 216 14.7.7 usb embedded device status register (dsr ) . . . . . . . . . 217 14.7.8 usb embedded device e ndpoint 0 data registers (de0d0?de0d7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.7.9 usb embedded device e ndpoint 1/2 data registers (de1d0?de1d7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 section 15. multi-master iic interface (mmiic) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.5 multi-master iic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.5.1 multi-master iic address regist er (mmadr) . . . . . . . . . . 224 15.5.2 multi-master iic control register (mmcr) . . . . . . . . . . . . 225 15.5.3 multi-master iic ma ster control register (mimcr) . . . . . . 226 15.5.4 multi-master iic stat us register (mmsr) . . . . . . . . . . . . . 228 table of contents mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor table of contents 15 15.5.5 multi-master iic data transm it register (mmdtr) . . . . . . 230 15.5.6 multi-master iic data receiv e register (mmdrr ) . . . . . . 231 15.6 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 232 section 16. ddc12ab interface 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16.5 ddc protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.6 ddc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.6.1 ddc address register (ddcadr) . . . . . . . . . . . . . . . . . . 238 16.6.2 ddc2 address register (ddc2adr ) . . . . . . . . . . . . . . . . 239 16.6.3 ddc control register (ddccr) . . . . . . . . . . . . . . . . . . . . 240 16.6.4 ddc master control register (ddcmcr) . . . . . . . . . . . . . 241 16.6.5 ddc status register (ddcsr) . . . . . . . . . . . . . . . . . . . . . 244 16.6.6 ddc data transmit register ( ddcdtr) . . . . . . . . . . . . . . 246 16.6.7 ddc data receive register (d dcdrr) . . . . . . . . . . . . . . 247 16.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 248 section 17. sync processor 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 17.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 17.5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.5.1 polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.1 hsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.2 vsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.3 composite sync polarity detect ion . . . . . . . . . . . . . . . . 256 17.5.2 sync signal counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table of contents data sheet mc68hc908ld64 ? rev. 3.0 16 table of contents freescale semiconductor 17.5.3 polarity controlled hout and vout outputs . . . . . . . . . . 257 17.5.4 clamp pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 17.5.5 low vertical frequency detect . . . . . . . . . . . . . . . . . . . . . 259 17.6 sync processor i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . 259 17.6.1 sync processor control & stat us register ( spcsr). . . . . 259 17.6.2 sync processor input/output control register (spiocr) . 261 17.6.3 vertical frequency registers (vfrs) . . . . . . . . . . . . . . . . . 263 17.6.4 hsync frequency registers (hfrs). . . . . . . . . . . . . . . . . . 265 17.6.5 sync processor control register 1 (spcr1). . . . . . . . . . . 267 17.6.6 h & v sync output control re gister (hvocr) . . . . . . . . . 268 17.7 system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 section 18. on-scr een display (osd) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.4 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.5 osd flash font memory map . . . . . . . . . . . . . . . . . . . . . . . 275 18.6 osd screen memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 18.7 osd module i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . .277 18.7.1 osd control register (osdcr) . . . . . . . . . . . . . . . . . . . . 277 18.7.2 osd status register (osdsr) . . . . . . . . . . . . . . . . . . . . . 278 18.7.3 osd data registers (osddrh: osddrl) . . . . . . . . . . . . 279 18.7.4 osd row address register (osdr ar) . . . . . . . . . . . . . . 280 18.7.5 osd column address register (osdcar). . . . . . . . . . . . 280 18.7.6 osd flash even high byte write buffer (osdehbuf) . 281 18.8 osd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.8.1 osd display registers (attri bute and code re gisters) . . . 282 18.8.2 row attribute registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.8.3 control, window, and pattern registers . . . . . . . . . . . . . . 283 18.8.3.1 window register s 1, 2, 3, 4 . . . . . . . . . . . . . . . . . . . . . . 284 18.8.3.2 vertical delay control register . . . . . . . . . . . . . . . . . . . 285 18.8.3.3 horizontal delay c ontrol register . . . . . . . . . . . . . . . . . 286 table of contents mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor table of contents 17 18.8.3.4 character height control register . . . . . . . . . . . . . . . . . 286 18.8.3.5 frame control regist ers . . . . . . . . . . . . . . . . . . . . . . . . 288 section 19. input/output (i/o) ports 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 19.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 298 19.3.3 port a options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 19.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 301 19.4.3 port b options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.3 port c options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.6.3 port d options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 19.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.7.3 port e options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 section 20. external interrupt (irq) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 table of contents data sheet mc68hc908ld64 ? rev. 3.0 18 table of contents freescale semiconductor 20.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.5 irq status and contro l register (intscr) . . . . . . . . . . . . . . 319 20.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 320 section 21. keyboard in terrupt module (kbi) 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 21.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 21.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 21.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 326 21.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 327 21.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 21.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 328 section 22. computer op erating properly (cop) 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 22.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 22.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 table of contents mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor table of contents 19 22.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 332 22.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 22.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 22.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 334 section 23. break module (brk) 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 23.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 338 23.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .338 23.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 338 23.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 338 23.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 23.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 23.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 23.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 23.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 339 23.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 342 section 24. electrical specifications 24.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 table of contents data sheet mc68hc908ld64 ? rev. 3.0 20 table of contents freescale semiconductor 24.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 344 24.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 345 24.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 24.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 346 24.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 24.8 timer interface module characterist ics . . . . . . . . . . . . . . . . . 347 24.9 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 24.10 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 348 24.11 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.12 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 349 24.12.1 usb low speed sour ce electrical characte ristics . . . . . . 350 24.12.2 usb high speed source electric al characteristics . . . . . . 351 24.12.3 hub repeater electrical characte ristics . . . . . . . . . . . . . . 352 24.12.4 usb signaling levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 24.13 ddc12ab/mmiic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 24.13.1 ddc12ab/mmiic interface input signal timing . . . . . . . . 354 24.13.2 ddc12ab/mmiic interface output signal timing . . . . . . . 354 24.14 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 355 section 25. mechanic al specifications 25.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 25.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 358 section 26. ordering information 26.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 26.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor list of figures 21 data sheet ? mc68hc908ld64 list of figures figure title page 1-1 mc68hc908ld64 mcu block diagram. . . . . . . . . . . . . . . . . . 35 1-2 64-pin qfp pin assi gnment . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .45 4-1 flash i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 64 4-2 47,616-byte flash contro l register (flcr) . . . . . . . . . . . . . 66 4-3 13k-byte flash control register (flcr1) . . . . . . . . . . . . . . . 66 4-4 osd flash even high byte writ e buffer (osdehbuf) . . . . 67 4-5 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 71 4-6 47,616-byte flash block protect register ( flbpr). . . . . . . . 72 4-7 13k-byte flash block protect regi ster 1 (flbpr1) . . . . . . . 72 4-8 flash block protec t start address . . . . . . . . . . . . . . . . . . . . .73 5-1 configuration register (config). . . . . . . . . . . . . . . . . . . . . . . 76 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 82 7-1 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .96 8-1 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8-2 cgm i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 102 8-3 pll control register (pc tl) . . . . . . . . . . . . . . . . . . . . . . . . . 105 8-4 pll bandwidth control register (pbwc) . . . . . . . . . . . . . . . 107 list of figures data sheet mc68hc908ld64 ? rev. 3.0 22 list of figures freescale semiconductor figure title page 8-5 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . . . 108 8-6 h&v sync output cont rol register (hvocr) . . . . . . . . . . . . 110 9-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .116 9-3 osc clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 9-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9-8 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9-9 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9-10 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 126 9-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . 129 9-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . . 129 9-14 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9-15 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . 132 9-16 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 132 9-17 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9-18 stop mode recovery fr om interrupt or break . . . . . . . . . . . . . 133 9-19 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 134 9-20 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 135 9-21 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 136 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10-2 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 10-5 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 11-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11-2 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 156 11-3 tim status and control register (tsc ) . . . . . . . . . . . . . . . . . 161 11-4 tim counter register s (tcnth:tcntl) . . . . . . . . . . . . . . . . 163 11-5 tim counter modulo registers (tmodh:tmodl) . . . . . . . . . 164 list of figures mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor list of figures 23 figure title page 11-6 tim channel status and contro l registers (tsc0:tsc1) . . . 165 11-7 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11-8 tim channel registers (tch0h/l:t ch1h/l). . . . . . . . . . . . . 169 12-1 pwm i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 172 12-2 pwm data registers 0 to 7 (0pw m?7pwm) . . . . . . . . . . . . . 173 12-3 pwm control register (pwmcr). . . . . . . . . . . . . . . . . . . . . . 174 12-4 8-bit pwm output waveforms . . . . . . . . . . . . . . . . . . . . . . . . 175 13-1 adc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 13-3 adc status and control register (adscr) . . . . . . . . . . . . . . 183 13-4 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13-5 adc input clock register (adiclk) . . . . . . . . . . . . . . . . . . . 185 14-1 usb i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 190 14-2 usb module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14-3 usb hub root port control register (hrpcr) . . . . . . . . . . . 194 14-4 usb hub downstream port control registers (hdp1cr?hdp4cr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14-5 usb sie timing interrupt register (sietir) . . . . . . . . . . . . . 198 14-6 usb sie timing status register (sietsr) . . . . . . . . . . . . . . 200 14-7 usb hub address regist er (haddr) . . . . . . . . . . . . . . . . . . 202 14-8 usb hub interrupt regist er 0 (hir0) . . . . . . . . . . . . . . . . . . . 203 14-9 usb hub control register 0 (hcr0) . . . . . . . . . . . . . . . . . . . 205 14-10 usb hub endpoint 1 control and data register (hcdr) . . . 206 14-11 usb hub status register (hsr) . . . . . . . . . . . . . . . . . . . . . . 208 14-12 usb hub endpoint 0 data regi sters (he0d0?he0d7) . . . . . 209 14-13 usb embedded de vice address register (daddr) . . . . . . . 210 14-14 usb embedded devi ce interrupt regi ster 0 (dir0). . . . . . . . 210 14-15 usb embedded devi ce interrupt regi ster 1 (dir1). . . . . . . . 212 14-16 usb embedded devi ce control register 0 (dcr0). . . . . . . . 213 14-17 usb embedded devi ce control register 1 (dcr1). . . . . . . . 215 14-18 usb embedded devi ce control register 2 (dcr2). . . . . . . . 216 14-19 usb embedded devi ce status register (dsr ) . . . . . . . . . . . 217 14-20 usb embedded de vice endpoint 0 data registers (de0d0?de0d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 list of figures data sheet mc68hc908ld64 ? rev. 3.0 24 list of figures freescale semiconductor figure title page 14-21 usb embedded devi ce endpoint 1/2 data registers (de1d0?de1d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15-1 mmiic i/o register summa ry. . . . . . . . . . . . . . . . . . . . . . . . . 223 15-2 multi-master iic address register (mmadr). . . . . . . . . . . . . 224 15-3 multi-master iic control register (mmcr). . . . . . . . . . . . . . . 225 15-4 multi-master iic master control register (mimcr) . . . . . . . . 226 15-5 multi-master iic status register (mmsr) . . . . . . . . . . . . . . . 228 15-6 multi-master iic data transmit register (mmdtr) . . . . . . . . 230 15-7 multi-master iic data receive r egister (mmdrr) . . . . . . . . 231 15-8 data transfer sequenc es for master/slave transmit/receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 233 16-1 ddc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16-2 ddc address register (ddcadr). . . . . . . . . . . . . . . . . . . . . 238 16-3 ddc2 address register (ddc2adr). . . . . . . . . . . . . . . . . . . 239 16-4 ddc control register (ddccr). . . . . . . . . . . . . . . . . . . . . . . 240 16-5 ddc master control register (ddc mcr) . . . . . . . . . . . . . . . 241 16-6 ddc status register (d dcsr) . . . . . . . . . . . . . . . . . . . . . . .244 16-7 ddc data transmit regi ster (ddcdtr) . . . . . . . . . . . . . . . . 246 16-8 ddc data receive regi ster (ddcdrr) . . . . . . . . . . . . . . . . 247 16-9 data transfer sequenc es for master/slave transmit/receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17-1 sync processor i/o register summar y . . . . . . . . . . . . . . . . . 254 17-2 sync processor block diagram . . . . . . . . . . . . . . . . . . . . . . .255 17-3 clamp pulse output timing . . . . . . . . . . . . . . . . . . . . . . . . . . 258 17-4 sync processor control & status register (spcsr) . . . . . . . 259 17-5 sync processor input/output cont rol register (spiocr) . . . 261 17-6 vertical frequency high register . . . . . . . . . . . . . . . . . . . . . . 263 17-7 vertical frequency low register . . . . . . . . . . . . . . . . . . . . . . 263 17-8 hsync frequency high regist er . . . . . . . . . . . . . . . . . . . . . . . 265 17-9 hsync frequency low regist er . . . . . . . . . . . . . . . . . . . . . . .265 17-10 sync processor control register 1 (spcr1) . . . . . . . . . . . . . 267 17-11 h&v sync output control register (hvocr) . . . . . . . . . . . . 268 list of figures mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor list of figures 25 figure title page 18-1 on-screen display i/o register summ ary . . . . . . . . . . . . . . . 273 18-2 osd block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18-3 memory map of osd flash fonts . . . . . . . . . . . . . . . . . . . .275 18-4 memory map of osd regist ers . . . . . . . . . . . . . . . . . . . . . . .276 18-5 osd control register (o sdcr). . . . . . . . . . . . . . . . . . . . . . . 277 18-6 osd status register (o sdsr) . . . . . . . . . . . . . . . . . . . . . . .278 18-7 osd data register hi gh (osddrh) . . . . . . . . . . . . . . . . . . . 279 18-8 osd data register low (osddrl) . . . . . . . . . . . . . . . . . . . .279 18-9 osd row address register (osdrar) . . . . . . . . . . . . . . . . 280 18-10 osd column address register (osdcar) . . . . . . . . . . . . . . 280 18-11 osd flash even high byte wr ite buffer (osdehbuf) . . . 281 18-12 osd font even byte buffe r . . . . . . . . . . . . . . . . . . . . . . . . . . 281 18-13 character font matrix height ex pansion by ch[3:0] . . . . . . . 287 18-14 display character height . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 19-1 port i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .294 19-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 298 19-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 19-5 keyboard interrupt enable register (kier) . . . . . . . . . . . . . . 299 19-6 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19-7 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 301 19-8 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 19-9 pwm control register (pwmcr). . . . . . . . . . . . . . . . . . . . . . 302 19-10 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19-11 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 304 19-12 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19-13 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19-14 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 307 19-15 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19-16 port d control register (pdcr) . . . . . . . . . . . . . . . . . . . . . . . 309 19-17 port e data register (pte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19-18 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 312 19-19 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 19-20 port e control register (pecr) . . . . . . . . . . . . . . . . . . . . . . . 313 list of figures data sheet mc68hc908ld64 ? rev. 3.0 26 list of figures freescale semiconductor figure title page 20-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 317 20-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .317 20-3 irq status and contro l register (intscr) . . . . . . . . . . . . . . 319 21-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .322 21-2 keyboard interrupt module block di agram. . . . . . . . . . . . . . . 323 21-3 keyboard status and control register (kbscr) . . . . . . . . . . 326 21-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 327 22-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 22-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 332 22-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 333 23-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 337 23-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 337 23-3 break status and control register (brkscr). . . . . . . . . . . . 339 23-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 340 23-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 340 23-6 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 341 23-7 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 342 24-1 mmiic signal timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 25-1 64-pin qfp (case #840b) . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor list of tables 27 data sheet ? mc68hc908ld64 list of tables table title page 1-1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4-1 flash memory array summary . . . . . . . . . . . . . . . . . . . . . . . 65 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8-1 free-running hsout, vsout, de, and dclk settings . . . 102 8-2 vco frequency multiplier (n) selectio n. . . . . . . . . . . . . . . . . 109 9-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9-3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9-4 sim registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10-1 monitor mode signal requirements and options . . . . . . . . . . 141 10-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10-3 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 144 10-4 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 145 10-5 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 145 10-6 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 146 10-7 readsp (read stack po inter) command . . . . . . . . . . . . . . . 146 10-8 run (run user program) command . . . . . . . . . . . . . . . . . . . 147 10-9 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 147 11-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 167 list of tables data sheet mc68hc908ld64 ? rev. 3.0 28 list of tables freescale semiconductor table title page 12-1 pwm channels and port i/o pins. . . . . . . . . . . . . . . . . . . . . . 174 13-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 13-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 14-1 usb i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15-2 baud rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16-2 baud rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 17-2 sync output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 17-3 sync output polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 17-4 atpol, vinvo, and hinvo setting. . . . . . . . . . . . . . . . . . . .261 17-5 sample vertical frame frequencies . . . . . . . . . . . . . . . . . . . 264 17-6 clamp pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 17-7 hsync polarity detect ion pulse width . . . . . . . . . . . . . . . . . 267 17-8 atpol, vinvo, and hinvo setting. . . . . . . . . . . . . . . . . . . .268 17-9 free-running hsout, vsout, de, and dclk settings . . . 269 18-1 shadow width setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 18-2 shadow width setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 19-1 port control register bits summary. . . . . . . . . . . . . . . . . . . .296 19-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 19-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19-4 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19-5 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19-6 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 21-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 24-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 344 list of tables mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor list of tables 29 table title page 24-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 24-3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 24-4 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 346 24-5 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 24-6 tim characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 24-7 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 24-8 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 348 24-9 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 24-10 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 349 24-11 usb low speed source electrical characterist ics. . . . . . . . . 350 24-12 usb high speed source electrical characteristics . . . . . . . . 351 24-13 hub repeater electrical characteristics . . . . . . . . . . . . . . . . 352 24-14 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 24-15 ddc12ab/mmiic interface input si gnal timing. . . . . . . . . . . 354 24-16 ddc12ab/mmiic interface output signal timing . . . . . . . . . 354 24-17 flash memory electrical characteri stics . . . . . . . . . . . . . . . 355 26-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 list of tables data sheet mc68hc908ld64 ? rev. 3.0 30 list of tables freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor general description 31 data sheet ? mc68hc908ld64 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 1.2 introduction the mc68hc908ld64 is a member of the low-cost, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. with special modules such as t he sync processor, on-screen display module, analog-to-digital converter, pulse modulator module, ddc12ab interface, multi-master iic interface, and universal serial bus interface, the mc68hc908ld64 is desig ned specifically for us e in digital monitor systems. general description data sheet mc68hc908ld64 ? rev. 3.0 32 general description freescale semiconductor 1.3 features features of the mc 68hc908ld64 mcu include the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families low-power design; fully st atic with stop and wait modes 3.3v operating voltage 6mhz internal bus frequency; with 24mhz external crystal 60,928 bytes of on-chip fl ash memory with security 1 feature 2,048 bytes of on-chip r andom access memory (ram) 39 general-purpose input/out put (i/o) pins, including: ? 38 shared-function i/o pins ? 8-bit keyboard interrupt port 2-channel, 16-bit timer interface module (tim) with selectable input capture, output com pare, and pwm capability on one channel 6-channel, 8-bit analog-to-d igital converter (adc) 8-channel, 8-bit pulse wi dth modulator (pwm) sync signal processor with the following features: ? horizontal and vertic al frequency counters ? low vertical frequency indicator (40.7hz) ? polarity controlled hsync and vsync outputs from separate sync or composite sync inputs ? internal generated fr ee-running hsync, vsync, de, and dclk ? clamp pulse output to the external pre-amp chip on screen display (osd) and full screen pattern display 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. general description features mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor general description 33 full universal serial bus (usb) specification 1.1, composite hub with embedded func tions, including: ? one 12mhz upstream port ? four 12mhz/1.5mhz downstream ports ? one hub control endpoi nt with 8-byte tr ansmit buffer and 8-byte receive buffer ? one hub interrupt endpoint with 1-byte transmit buffer ? one device control endpoint with 8-byte transmit buffer and 8-byte receive buffer ? two device interrupt endpoints wi th shared 8-byte transmit buffer ddc12ab 1 module with the following: ? ddc1 hardware ? multi-master iic 2 hardware for ddc2ab; with dual address additional multi- master iic module in-system programming capabi lity using usb or ddc12ab communication, or standard serial link on pta0 pin system protection features: ? optional computer operati ng properly (cop) reset ? illegal opcode detection with reset ? illegal address detection with reset master reset pin (with inter nal pull-up) and power-on reset irq interrupt pin with internal pull-up and schmi tt-trigger input 64-pin quad flat pack (qfp) package 1. ddc is a vesa bus standard. 2. iic is a proprietary philips interface bus. general description data sheet mc68hc908ld64 ? rev. 3.0 34 general description freescale semiconductor features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc908ld64. general description mcu block diagram mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor general description 35 figure 1-1. mc68hc908l d64 mcu block diagram system integration module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 80 bytes user flash ? 60,928 bytes user ram ? 2,048 bytes monitor rom ? 1,024+464 bytes user flash vector space ? 32 bytes external irq module ddrd portd internal bus rst irq computer operating properly module ptd7/iicsda ? ptd6/iicscl ? ptd5/ddcsda ? ptd4/ddcscl ? ptd3/hout ptd2/vout clamp/tch0 power-on reset module power vss1 vdd1 vss2 vdd2 hsync ?? vsync ?? porta ddra pta7/kbi7 ptd1/de ptd0/dclk universal serial bus interface module hub controller ds port 4 ? pin is +5v open-drain ?? pin is +5v input security module monitor mode entry module ddc12ab interface module 2-channel timer interface module multi-master iic interface module sync processor module free-run panel timing module keyboard interrupt module pulse width modulator module monitor module 8-bit analog-to-digital converter module pta0/kbi0 : portb ddrb ptb7/pwm7 ptb0/pwm0 : portc ddrc ptc5/adc5 ptc0/adc0 : ptc6 clock generator module osc1 osc2 cgmxfc 24-mhz oscillator phase-locked loop ddre porte pte7/dminus4 pte6/dplus4 pte5/dminus3 pte4/dplus3 pte3/dminus2 pte2/dplus2 pte1/dminus1 pte0/dplus1 dminus0 dplus0 on-screen display module phsync ?? pvsync ?? pclk ?? osdr osdg osdb fbkg and ds port 3 ds port 2 ds port 1 us port vssa vdda adc reference vrl vrh general description data sheet mc68hc908ld64 ? rev. 3.0 36 general description freescale semiconductor 1.5 pin assignments figure 1-2. 64-pin qfp pin assignment pte2/dplus2 pte0/dplus1 ptc3/adc3 ptb5/pwm5 dminus0 dplus0 vdd1 vssa osc2 osc1 vdda pte1/dminus1 pte3/dminus2 pte4/dplus3 pte5/dminus3 pte6/dplus4 pte7/dminus4 cgmxfc pta3/kbi3 pta2/kbi2 pta1/kbi1 pta0/kbi0 vdd2 ptb7/pwm7 ptb6/pwm6 ptb4/pwm4 ptb3/pwm3 ptb2/pwm2 ptb1/pwm1 ptb0/pwm0 ptd7iicsda ptd6/iicscl ptd5/ddcsda ptc4/adc4 vss2 ptc5/adc5 ptc6 pta7/kbi7 pta6/kbi6 pta5/kbi5 pta4/kbi4 irq rst vrh vrl ptc0/adc0 ptc1/adc1 ptc2/adc2 vsync vss1 clamp/tch0 hsync pvsync phsync pclk osdr osdg osdb fbkg ptd0/dclk ptd1/de ptd2/vout ptd3/hout ptd4/ddcscl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 general description pin functions mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor general description 37 1.6 pin functions description of the pin f unctions are provided in table 1-1 . table 1-1. pin functions pin name pin description vdd1, vdd2 power supply input to the mcu. vss1, vss2 power supply ground. vdda power supply input for analog circuits. vssa power supply ground for analog circuits. osc1, osc2 crystal connections to the on-chip oscillator. an external clock can be connected directly to osc1; with osc2 floating. see section 7. oscillator (osc) . rst external reset pin; active low; with internal pull-up and schmitt trigger input. it is driven low when any internal reset source is asserted. see section 9. system integration module (sim) . irq external irq pin; with schmitt trigger input and internal pull-up. this pin is also used for mode entry selection. see section 20. external interrupt (irq) and section 9. system integration module (sim) . cgmxfc external filter capacitor connection for the cgm module. see section 8. clock generator module (cgm) . vsync vsync input to the sync processor. this pin is rated at +5v. see section 17. sync processor . hsync hsync input to the sync processor. this pin is rated at +5v. see section 17. sync processor . pta7/kbi7?pta0/kbi0 these are shared function, bidirectional i/o port pins. each pin contains a pull-up device to vdd when it is configured as an external keyboard interrupt pin. see section 19. input/output (i/o) ports and section 21. keyboard interrupt module (kbi) . general description data sheet mc68hc908ld64 ? rev. 3.0 38 general description freescale semiconductor ptb7/pwm7?ptb0/pwm0 these are shared-function, bidirectional i/o port pins. each pin can be configured as a standard i/o pin or a pwm output channel. see section 19. input/output (i/o) ports and section 12. pulse width modulator (pwm) . vrh high voltage referenc e input to adc module. vrl low voltage reference input to adc module. ptc6 this pin is a standard bidirectional i/o pin. see section 19. input/output (i/o) ports . ptc5/adc5?ptc0/adc0 these are shared-function, bidirectional i/o port pins. each pin can be configured as a standard i/o pin or an adc input channel. see section 19. input/output (i/o) ports and section 13. analog-to- digital converter (adc) . ptd7/iicsda this is a shared-function pin. it can be configured as a standard i/o pin or the data line of the multi- master iic module. this pin is +5v open-drain when configured as output. see section 19. input/output (i/o) ports and section 15. multi-master iic interface (mmiic) . ptd6/iicscl this is a shared function pin. it can be configured as a standard i/o pin or the clock line of the multi- master iic module. this pin is +5v open-drain when configured as output. see section 19. input/output (i/o) ports and section 15. multi-master iic interface (mmiic) . ptd5/ddcsda this is a shared function pin. it can be configured as a standard i/o pin or the data line of the ddc12ab module. this pin is +5v open-drain when configured as output. see section 19. input/output (i/o) ports and section 16. ddc12ab interface . ptd4/ddcscl this is a shared function pin. it can be configured as a standard i/o pin or the clock line of the ddc12ab module. this pin is +5v open-drain when configured as output. see section 19. input/output (i/o) ports and section 16. ddc12ab interface . table 1-1. pin fun ctions (continued) pin name pin description general description pin functions mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor general description 39 note: any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68hc908ld64 do not require termination, termination is recommended to reduce the possibility of static damage. ptd3/hout ptd2/vout ptd1/de ptd0/dclk these are shared function, bidirectional i/o port pins. these pins can be configured as standard i/o pins or free-run timing output signals. see section 19. input/output (i/o) ports and section 17. sync processor . clamp/tch0 this is shared function pins. this tim channel 0 i/o pin can be configured as the sync processor clamp output pin. see section 11. timer interface module (tim) and section 17. sync processor . pvsync vsync input to the on-screen display module. this pin is rated at +5v. see section 18. on-screen display (osd) . phsync hsync input to the on-screen display module. this pin is rated at +5v. see section 18. on-screen display (osd) . pclk pixel clock input to the on-screen display module. this pin is rated at +5v. see section 18. on-screen display (osd) . osdr osdg osdb r, g, and b output of the on-screen display module. see section 18. on-screen display (osd) . fbkg pixel-enable output of the on-screen display module. see section 18. on-screen display (osd) . pte7/dminus4 pte6/dplus4 pte5/dminus3 pte4/4dplus3 pte3/dminus2 pte2/dplus2 pte1/dminus1 pte0/dplus1 these are shared function, bidirectional i/o port pins. these pins can be configured as standard i/o pins or downstream data pins of usb module. see section 19. input/output (i/o) ports and section 14. universal se rial bus module (usb) . dplus0 dminus0 data pins of usb module upstream port. see section 14. universal serial bus module (usb) . table 1-1. pin fun ctions (continued) pin name pin description general description data sheet mc68hc908ld64 ? rev. 3.0 40 general description freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 41 data sheet ? mc68hc908ld64 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 60,928 bytes of flash memory 2,048 bytes of random-a ccess memory (ram) 32 bytes of user-defined vectors 1,024 + 464 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented locati on can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. memory map data sheet mc68hc908ld64 ? rev. 3.0 42 memory map freescale semiconductor 2.4 reserved memory locations accessing a reserved location can hav e unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserv ed or with the letter r. 2.5 input/output (i/o) section most of the control, st atus, and data registers ar e in the zero page area of $0000?$007f. additional i/o registers have these addresses: $fe00; sim break st atus register, sbsr $fe01; sim reset st atus register, srsr $fe02; reserved $fe03; sim break flag control register, sbfcr $fe04; interrupt stat us register 1, int1 $fe05; interrupt stat us register 2, int2 $fe06; reserved $fe07; 47,616 bytes flash control register, flcr $fe08; 47,616 bytes flash blo ck protect register, flbpr $fe09; reserved $fe0a; 13k-bytes flash control register, flcr1 $fe0b; 13k-bytes flash blo ck protect register, flbpr1 $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; reserved $ffff; cop control register, copctl data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 43 $0000 i/o registers 128 bytes $007f $0080 ram 1,024 bytes $047f $0480 unimplemented 896 bytes $07ff $0800 osd ram 1,024 bytes $0bff $0c00 flash memory 1,024 bytes (8 128-byte blocks) $0fff $1000 osd flash memory 12,288 bytes (24 512-byte blocks) $3fff $4000 flash memory 47,616 bytes (93 512-byte blocks) $f9ff $fa00 monitor rom 1,024 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) figure 2-1. memory map memory map data sheet mc68hc908ld64 ? rev. 3.0 44 memory map freescale semiconductor $fe05 interrupt status register 2 (int2) $fe06 reserved $fe07 47,616 bytes flash control register (flcr) $fe08 47,616 bytes flash block protect register (flbpr) $fe09 reserved $fe0a 13k-bytes flash control register (flcr1) $fe0b 13k-bytes flash block protect register (flbpr1) $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and co ntrol register (brkscr) $fe0f reserved $fe10 monitor rom 464 bytes $ffdf $ffe0 flash vectors 32 bytes $ffff figure 2-1. memory map (continued) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 45 addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 46 memory map freescale semiconductor $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000b unimplemented read: write: reset:00000000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 15) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 47 $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0016 ddc master control register (ddcmcr) read: alif nakif bb mast mrw br2 br1 br0 write: reset:00000000 $0017 ddc address register (ddcadr) read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 $0018 ddc control register (ddccr) read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 $0019 ddc status register (ddcsr) read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 $001a ddc data transmit register (ddcdtr) read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 $001b ddc data receive register (ddcdrr) read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 $001c ddc2 address register (ddc2adr) read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 $001d unimplemented read: write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 48 memory map freescale semiconductor $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 $001f configuration register (config) ? read: 0000 ssrec coprs stop copd write: reset:00000000 ? one-time writable regi ster after each reset. $0020 usb embedded device endpoint 0 data reg. 0 (de0d0) read: de0r07 de0r06 de0r05 de0r 04 de0r03 de0r02 de0r01 de0r00 write: de0t07 de0t06 de0t05 de0t 04 de0t03 de0t02 de0t01 de0t00 reset: indeterminate after reset $0021 usb embedded device endpoint 0 data reg. 1 (de0d1) read: de0r17 de0r16 de0r15 de0r 14 de0r13 de0r12 de0r11 de0r10 write: de0t17 de0t16 de0t15 de0t 14 de0t13 de0t12 de0t11 de0t10 reset: indeterminate after reset $0022 usb embedded device endpoint 0 data reg. 2 (de0d2) read: de0r27 de0r26 de0r25 de0r 24 de0r23 de0r22 de0r21 de0r20 write: de0t27 de0t26 de0t25 de0t 24 de0t23 de0t22 de0t21 de0t20 reset: indeterminate after reset $0023 usb embedded device endpoint 0 data reg. 3 (de0d3) read: de0r37 de0r36 de0r35 de0r 34 de0r33 de0r32 de0r31 de0r30 write: de0t37 de0t36 de0t35 de0t 34 de0t33 de0t32 de0t31 de0t30 reset: indeterminate after reset $0024 usb embedded device endpoint 0 data reg. 4 (de0d4) read: de0r47 de0r46 de0r45 de0r 44 de0r43 de0r42 de0r41 de0r40 write: de0t47 de0t46 de0t45 de0t 44 de0t43 de0t42 de0t41 de0t40 reset: indeterminate after reset $0025 usb embedded device endpoint 0 data reg. 5 (de0d5) read: de0r57 de0r56 de0r55 de0r 54 de0r53 de0r52 de0r51 de0r50 write: de0t57 de0t56 de0t55 de0t 54 de0t53 de0t52 de0t51 de0t50 reset: indeterminate after reset $0026 usb embedded device endpoint 0 data reg. 6 (de0d6) read: de0r67 de0r66 de0r65 de0r 64 de0r63 de0r62 de0r61 de0r60 write: de0t67 de0t66 de0t65 de0t 64 de0t63 de0t62 de0t61 de0t60 reset: indeterminate after reset $0027 usb embedded device endpoint 0 data reg. 7 (de0d7) read: de0r77 de0r76 de0r75 de0r 74 de0r73 de0r72 de0r71 de0r70 write: de0t77 de0t76 de0t75 de0t 74 de0t73 de0t72 de0t71 de0t70 reset: indeterminate after reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 15) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 49 $0028 usb embedded device endpoint 1/2 data reg. 0 (de1d0) read: write: de1t07 de1t06 de1t05 de1t 04 de1t03 de1t02 de1t01 de1t00 reset: indeterminate after reset $0029 usb embedded device endpoint 1/2 data reg. 1 (de1d1) read: write: de1t17 de1t16 de1t15 de1t 14 de1t13 de1t12 de1t11 de1t10 reset: indeterminate after reset $002a usb embedded device endpoint 1/2 data reg. 2 (de1d2) read: write: de1t27 de1t26 de1t25 de1t 24 de1t23 de1t22 de1t21 de1t20 reset: indeterminate after reset $002b usb embedded device endpoint 1/2 data reg. 3 (de1d3) read: write: de1t37 de1t36 de1t35 de1t 34 de1t33 de1t32 de1t31 de1t30 reset: indeterminate after reset $002c usb embedded device endpoint 1/2 data reg. 4 (de1d4) read: write: de1t47 de1t46 de1t45 de1t 44 de1t43 de1t42 de1t41 de1t40 reset: indeterminate after reset $002d usb embedded device endpoint 1/2 data reg. 5 (de1d5) read: write: de1t57 de1t56 de1t55 de1t 54 de1t53 de1t52 de1t51 de1t50 reset: indeterminate after reset $002e usb embedded device endpoint 1/2 data reg. 6 (de1d6) read: write: de1t67 de1t66 de1t65 de1t 64 de1t63 de1t62 de1t61 de1t60 reset: indeterminate after reset $002f usb embedded device endpoint 1/2 data reg. 7 (de1d7) read: write: de1t77 de1t76 de1t75 de1t 74 de1t73 de1t72 de1t71 de1t70 reset: indeterminate after reset $0030 usb hub endpoint 0 data register 0 (he0d0) read: he0r07 he0r06 he0r05 he0r 04 he0r03 he0r02 he0r01 he0r00 write: he0t07 he0t06 he0t05 he0t 04 he0t03 he0t02 he0t01 he0t00 reset: indeterminate after reset $0031 usb hub endpoint 0 data register 1 (he0d1) read: he0r17 he0r16 he0r15 he0r 14 he0r13 he0r12 he0r11 he0r10 write: he0t17 he0t16 he0t15 he0t 14 he0t13 he0t12 he0t11 he0t10 reset: indeterminate after reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 50 memory map freescale semiconductor $0032 usb hub endpoint 0 data register 2 (he0d2) read: he0r27 he0r26 he0r25 he0r 24 he0r23 he0r22 he0r21 he0r20 write: he0t27 he0t26 he0t25 he0t 24 he0t23 he0t22 he0t21 he0t20 reset: indeterminate after reset $0033 usb hub endpoint 0 data register 3 (he0d3) read: he0r37 he0r36 he0r35 he0r 34 he0r33 he0r32 he0r31 he0r30 write: he0t37 he0t36 he0t35 he0t 34 he0t33 he0t32 he0t31 he0t30 reset: indeterminate after reset $0034 usb hub endpoint 0 data register 4 (he0d4) read: he0r47 he0r46 he0r45 he0r 44 he0r43 he0r42 he0r41 he0r40 write: he0t47 he0t46 he0t45 he0t 44 he0t43 he0t42 he0t41 he0t40 reset: indeterminate after reset $0035 usb hub endpoint 0 data register 5 (he0d5) read: he0r57 he0r56 he0r55 he0r 54 he0r53 he0r52 he0r51 he0r50 write: he0t57 he0t56 he0t55 he0t 54 he0t53 he0t52 he0t51 he0t50 reset: indeterminate after reset $0036 usb hub endpoint 0 data register 6 (he0d6) read: he0r67 he0r66 he0r65 he0r 64 he0r63 he0r62 he0r61 he0r60 write: he0t67 he0t66 he0t65 he0t 64 he0t63 he0t62 he0t61 he0t60 reset: indeterminate after reset $0037 usb hub endpoint 0 data register 7 (he0d7) read: he0r77 he0r76 he0r75 he0r 74 he0r73 he0r72 he0r71 he0r70 write: he0t77 he0t76 he0t75 he0t 74 he0t73 he0t72 he0t71 he0t70 reset: indeterminate after reset $0038 pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 $0039 pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset:00000000 $003a pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 $003b adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 15) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 51 $003c adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $003d adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 $003e unimplemented read: write: reset: $003f h & v sync output control register (hvocr) read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 $0040 sync processor control and status register (spcsr) read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 $0041 vertical frequency high register (vfhr) read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 $0042 vertical frequency low register (vflr) read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 $0043 hsync frequency high register (hfhr) read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 $0044 hsync frequency low register (hflr) read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 $0045 sync processor i/o control register (spiocr) read: vsyncs hsyncs coinv r r r bpor sout write: reset:000 00 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 52 memory map freescale semiconductor $0046 sync processor control register 1 (spcr1) read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:0000 00 $0047 usb embedded device control register 2 (dcr2) read: 0000 enable2 enable1 dstall2 dstall1 write: reset:00000000 $0048 usb embedded device address register (daddr) read: deven dadd6 dadd5 dadd4 dadd3 dadd2 dadd1 dadd0 write: reset:00000000 $0049 usb embedded device interrupt register 0 (dir0) read: txd0f rxd0f 0 0 txd0ie rxd0ie 00 write: txd0fr rxd0fr reset:00000000 $004a usb embedded device interrupt register 1 (dir1) read: txd1f 0 0 0 txd1ie 000 write: txd1fr reset:00000000 $004b usb embedded device control register 0 (dcr0) read: t0seq dstall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $004c usb embedded device control register 1 (dcr1) read: t1seq endadd tx1e 0 tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $004d usb embedded device status register (dsr) read: drseq dsetup dtx1st 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: dtx1str reset:00000000 $004e keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $004f keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 15) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 53 $0050 unimplemented read: write: reset: $0051 usb hub downstream port 1 control register (hdp1cr) read: pen1 lowsp1 rst1 resum1 susp1 0d1+d1? write: reset:000000xx $0052 usb hub downstream port 2 control register (hdp2cr) read: pen2 lowsp2 rst2 resum2 susp2 0d2+d2? write: reset:000000xx $0053 usb hub downstream port 3 control register (hdp3cr) read: pen3 lowsp3 rst3 resum3 susp3 0d3+d3? write: reset:000000xx $0054 usb hub downstream port 4 control register (hdp4cr) read: pen4 lowsp4 rst4 resum4 susp4 0d4+d4? write: reset:000000xx $0055 unimplemented read: write: reset: $0056 usb sie timing interrupt register (sietir) read: soff eof2f eopf tranf sofie eof2ie eopie tranie write: reset:00000000 $0057 usb sie timing status register (sietsr) read: rstf 0 lockf 00000 write: rstfr lockfr soffr eof2fr eopfr tranfr reset:0*0000000 $0058 usb hub address register (haddr) read: usben add6 add5 add4 add3 add2 add1 add0 write: reset:0*0000000 * rstf and usben are reset by a power-on reset (por) only. $0059 usb hub interrupt register 0 (hir0) read: txdf rxdf 0 0 txdie rxdie 00 write: txdfr rxdfr reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 54 memory map freescale semiconductor $005a unimplemented read: reset: reset: $005b usb hub control register 0 (hcr0) read: tseq stall0 txe rxe tpsiz3 tpsiz2 tpsiz1 tpsiz0 write: reset:00000000 $005c usb hub endpoint 1 control and data register (hcdr) read: stall1 pnew pchg5 pchg4 pchg3 pchg2 pchg1 pchg0 write: reset:00000000 $005d usb hub status register (hsr) read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: tx1str reset:xxx0xxxx $005e usb hub root port control register (hrpcr) read: 0 0 0 resum0 suspnd 0d0+d0? write: reset:000000xx $005f unimplemented read: write: reset: $0060 osd control register (osdcr) read: osdmen r osdrst clkinv clkph1 clkph0 halfclk osdien write: reset:0 000000 $0061 osd status register (osdsr) read: wrdy dendif write: reset: 1 0 $0062 osd data register low (osddrl) read: osdd7 osdd6 osdd5 osdd4 osdd3 osdd2 osdd1 osdd0 write: reset: unaffected by reset $0063 osd data register high (osddrh) read: osdd15 osdd14 osdd13 osdd12 osdd11 osdd10 osdd9 osdd8 write: reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 10 of 15) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 55 $0064 osd row address register (osdrar) read: rowa3 rowa2 rowa1 rowa0 write: reset: 0000 $0065 osd column address register (osdcar) read: cola4 cola3 cola2 cola1 cola0 write: reset: 00000 $0066 osd flash even high byte write buffer (osdehbuf) read: dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 write: reset: unaffected by reset $0067 unimplemented read: write: reset: $0068 port e control register (pecr) read: r usbds4e usbds3e usbds2e usbds1e write: reset: 0000 $0069 port d control register (pdcr) read: iicdate iicscle ddcdate ddcscle houte voute dee dclke write: reset:00000000 $006a multi-master iic master control register (mimcr) read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: 0 0 reset:00000000 $006b multi-master iic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $006c multi-master iic control register (mmcr) read: mmen mmien 00 mmtxak 000 write: reset:00000000 $006d multi-master iic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 11 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 56 memory map freescale semiconductor $006e multi-master iic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 $006f multi-master iic data receive register (mmdrr) read: mmrd7 mmrd6 mmrd5 mmrd4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 $0070 pwm0 data register (0pwm) read: 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 write: reset:00000000 $0071 pwm1 data register (1pwm) read: 1pwm4 1pwm3 1pwm2 1pwm1 1pwm0 1brm2 1brm1 1brm0 write: reset:00000000 $0072 pwm2 data register (2pwm) read: 2pwm4 2pwm3 2pwm2 2pwm1 2pwm0 2brm2 2brm1 2brm0 write: reset:00000000 $0073 pwm3 data register (3pwm) read: 3pwm4 3pwm3 3pwm2 3pwm1 3pwm0 3brm2 3brm1 3brm0 write: reset:00000000 $0074 pwm4 data register (4pwm) read: 4pwm4 4pwm3 4pwm2 4pwm1 4pwm0 4brm2 4brm1 4brm0 write: reset:00000000 $0075 pwm5 data register (5pwm) read: 5pwm4 5pwm3 5pwm2 5pwm1 5pwm0 5brm2 5brm1 5brm0 write: reset:00000000 $0076 pwm6 data register (6pwm) read: 6pwm4 6pwm3 6pwm2 6pwm1 6pwm0 6brm2 6brm1 6brm0 write: reset:00000000 $0077 pwm7 data register (7pwm) read: 7pwm4 7pwm3 7pwm2 7pwm1 7pwm0 7brm2 7brm1 7brm0 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 12 of 15) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 57 $0078 pwm control register (pwmcr) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 $0079 unimplemented read: write: reset: $007a unimplemented read: write: reset: $007b unimplemented read: write: reset: $007c unimplemented read: write: reset: $007d unimplemented read: write: reset: $007e unimplemented read: write: reset: $007f unimplemented read: write: reset: $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 13 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 58 memory map freescale semiconductor $fe01 sim reset status register (srsr) read: por pin cop ilop ilad usb 0 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 reserved read: rrrrrrrr write: reset: $fe07 47,616 bytes flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe08 47,616 bytes flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 $fe09 reserved read: rrrrrrrr write: reset: $fe0a 13k-bytes flash control register (flcr1) read: 0000 hven1 mass1 erase1 pgm1 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 14 of 15) memory map input/output (i/o) section mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor memory map 59 $fe0b 13k-bytes flash block protect register (flbpr1) read: bpr17 bpr16 bpr15 bpr14 bpr13 bpr12 bpr11 0 write: reset:00000000 $fe0c break address high register (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address low register (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: writing clears co p counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 15 of 15) memory map data sheet mc68hc908ld64 ? rev. 3.0 60 memory map freescale semiconductor . table 2-1. vector addresses vector priority vector address vector lowest if14 $ffe0 cgm pll interrupt vector (high) $ffe1 cgm pll interrupt vector (low) if13 $ffe2 keyboard interrupt vector (high) $ffe3 keyboard interrupt vector (low) if12 $ffe4 adc interrupt vector (high) $ffe5 adc interrupt vector (low) if11 $ffe6 osd interrupt vector (high) $ffe7 osd interrupt vector (low) if10 $ffe8 mmiic vector (high) $ffe9 mmiic vector (low) if9 $ffea sync processor vector (high) $ffeb sync processor vector (low) if8 $ffec tim overflow vector (high) $ffed tim overflow vector (low) if7 $ffee tim channel 1 vector (high) $ffef tim channel 1 vector (low) if6 $fff0 tim channel 0 vector (high) $fff1 tim channel 0 vector (low) if5 $fff2 ddc12ab vector (high) $fff3 ddc12ab vector (low) if4 $fff4 usb device interrupt vector (high) $fff5 usb device interrupt vector (low) if3 $fff6 usb hub interrupt vector (high) $fff7 usb hub interrupt vector (low) if2 $fff8 usb vector (high) $fff9 usb vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low) mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor random-access memory (ram) 61 data sheet ? mc68hc908ld64 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.2 introduction this section describes the 2, 048 bytes of ram (random-access memory). 3.3 functional description the ram is divided in to two blocks. addr esses $0080 through $047f are locations for general use. addresses $0800 th rough $0bff are locations for the osd display ram (see 18.6 osd screen memory map ). the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be an ywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 128 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently acce ss all page zero ram locations. page zero ram, therefore, provides i deal locations for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. random-access memory (ram) data sheet mc68hc908ld64 ? rev. 3.0 62 random-access memory (ram) freescale semiconductor note: for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor flash memory 63 data sheet ? mc68hc908ld64 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.4 flash control regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.1 osd flash even high byte write buffer (o sdehbuf) . . 67 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 flash block protect regi sters . . . . . . . . . . . . . . . . . . . . . . 72 flash memory data sheet mc68hc908ld64 ? rev. 3.0 64 flash memory freescale semiconductor 4.2 introduction this section describes the operat ion of the embedd ed flash memory. this memory can be r ead, programmed, and er ased from a single external supply. the program and er ase operations are enabled through the use of an internal charge pump. 4.3 functional description the mc68hc908ld64 flash memory contains two arrays: 13,312-byte array 47,616-byte array an additional 32 bytes of flash user vectors, $ffe0?$ffff, are in the same array as the 47 ,616-byte. the size, addr ess range, and memory usage of the arrays are summarized in table 4-1 . note: an erased bit reads as logic 1 and a programmed bit reads as logic 0. addr.register name bit 7654321bit 0 $fe07 47,616 bytes flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe08 47,616 bytes flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 $fe0a 13k-bytes flash control register (flcr1) read: 0000 hven1 mass1 erase1 pgm1 write: reset:00000000 $fe0b 13k-bytes flash block protect register (flbpr1) read: bpr17 bpr16 bpr15 bpr14 bpr13 bpr12 bpr11 0 write: reset:00000000 $0066 osd flash even high byte write buffer (osdehbuf) read: dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 write: reset: unaffected by reset figure 4-1. flash i/ o register summary flash memory functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor flash memory 65 each flash array is programmed an d erased through control bits in their respective memory mapped fla sh control registers, flcr and flcr1. the 13k-bytes array is programmed in double bytes. programming an odd address ($xxxx+1) location automatic ally programs the content in the osd flash even high byte write buffer (osdehbuf) to the even address ($xxxx) location. programming tools are available from freescale. contact your local freescale representative for more information. note: a security feature prevents vi ewing of the flash contents. 1 table 4-1. flash memory array summary 13,312 array 47,616 array bytes 1,024 12,288 47,616 32 address range $0c00?$0fff $1000?$3fff $4000?$f9ff $ffe0?$ffff minimum erase size 128 bytes 512 bytes 512 bytes 32 bytes by mass erase only usage user data or program osd fonts user program user vectors programming size double bytes in a 64-byte programming routine single bytes in a 64-byte programming routine related control registers flcr1 at $fe0a flbpr1 at $fe0b osdehbuf at $0066 flcr at $fe07 flbpr at $fe08 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. flash memory data sheet mc68hc908ld64 ? rev. 3.0 66 flash memory freescale semiconductor 4.4 flash control registers the two flash control registers control flash pr ogram and erase operations. this register c ontrols the 47, 616-byte array: this register controls the 13k-byte array: flcr1 is used with the osd flash even high byte write buffer (osdehbuf) in progra mming operations. see 4.4.1 osd flash even high byte write buffer (osdehbuf) . the following are bit definit ions for flcr and flcr1. hven ? high-volt age enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operati ons in the array. hv en can only be set if either pgm = 1 or erase = 1 and t he proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off address: $fe07 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 4-2. 47,616 -byte flash contro l register (flcr) address: $fe0a bit 7654321bit 0 read: 0000 hven1 mass1 erase1 pgm1 write: reset:00000000 = unimplemented figure 4-3. 13k-byte flash control register (flcr1) flash memory flash control registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor flash memory 67 mass ? mass erase control bit this read/write bit confi gures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = mass erase oper ation not selected erase ? erase control bit this read/write bit conf igures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit conf igures the memory fo r program operation. pgm is interlocked with the erase bit such t hat both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation not selected 4.4.1 osd flash ev en high byte write buffer (osdehbuf) dot[15:8] ? osd flash even high byte buffer these bits define the byte to be programmed to an even address location of the 13k-bytes array. the contents of this register will be automatically programmed to the even address ($xxxx) location when the odd address ($xxxx+1) is programm ed. reset has no effect on these bits. see 18.5 osd flash font memory map for osd font memory map. address: $0066 bit 76543210 read: dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 write: reset: unaffected by reset figure 4-4. osd flash even high byte write buffer (osdehbuf) flash memory data sheet mc68hc908ld64 ? rev. 3.0 68 flash memory freescale semiconductor 4.5 flash block erase operation the minimum erase size for the fla sh memory is one block, and is carried out by the block erase oper ation. for memory $0c00?$0fff, a block consists of 128 consecutive by tes starting from addresses $xx00 or $xx80. for memory $1000?$3fff and $4000?$f9ff, a block consists of 512 consecutive bytes starting from addresses $x000, $x200, $x400, $x600, $x800, $xa00, $xc00, or $xe00. note: the 32-byte user vector s, $ffe0?$ffff, cannot be erased by the block erase operation because of security reasons. mass erase is required to erase this block. use the following proc edure to erase a block of flash memory: 1. set the erase bit, a nd clear the mass bit in the flash control register. 2. write any data to any flash address within the block address range desired. 3. wait for a time, t nvs (min. 5 s) 4. set the hven bit. 5. wait for a time, t erase (min. 10ms) 6. clear the erase bit. 7. wait for a time, t nvh (min. 5 s) 8. clear the hven bit. 9. after a time, t rcv (min. 1 s), the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by code being executed from the same flash array that is being programmed or erased. while these operations must be performed in the order as shown, but other unrelated operati ons may occur between the steps. flash memory flash mass erase operation mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor flash memory 69 4.6 flash mass erase operation a mass erase operation erases an entire array of flash memory. the mc68hc908ld64 contains two flash memory arra ys, therefore, two mass erase operations ar e required to erase a ll flash memory in the device. mass erasing the 13k-byte array, erases all flash memory from $0800 to $3fff. mass erasing the 47,616-byt e array, erases all flash memory from $4000 to $ffff. use the following proc edure to erase an entir e flash memory array: 1. set both the erase bit, and the ma ss bit in the flash control register. 2. write any data to any flash address within the flash memory address range. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time, t erase (10ms). 6. clear the erase bit. 7. wait for a time, t nvhl (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s) , the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by code being executed from the same flash array that is being programmed or erased. while these operations must be performed in the order as shown, but other unrelated operati ons may occur between the steps. flash memory data sheet mc68hc908ld64 ? rev. 3.0 70 flash memory freescale semiconductor 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from a ddresses $xx00, $xx40, $xx80, and $xxc0. use this step-by-s tep procedure to program a row of flash memory ( figure 4-5 is a flowchart representation): note: in order to avoid program disturbs , the row must be erased before any byte on that ro w is programmed. 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write any data to any flash address within t he row address range desired. 3. wait for a time, t nvs (min. 5 s). 4. set the hven bit. 5. wait for a time, t pgs (min. 10 s). 6. for 47,616-byte array: write data to the flash address to be programmed. for 13k-byte array: write ev en address data to osdehbuf then write odd addre ss data to the odd flash address to be programmed. 7. wait for time, t prog (min. 20 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (min. 5 s). 11. clear the hven bit. 12. after time, t rcv (min 1 s), the memory can be accessed in read mode again. this program sequence is repeated th roughout the memory until all data is programmed. note: programming and erasing of flash locations c annot be performed by code being executed from the same flash array that is being programmed or erased. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. see 24.14 flash memory characteristics . flash memory flash program operation mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor flash memory 71 figure 4-5. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. write even byte to osd flash even high byte write buffer at $0066. write odd byte to the flash address to be programmed. for 47,616 bytes array for 13k-bytes array flash memory data sheet mc68hc908ld64 ? rev. 3.0 72 flash memory freescale semiconductor 4.8 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register for ea ch array (flbpr and fl bpr1). the block protect register determines t he range of the flash me mory which is to be protected. the range of t he protected area st arts from a location defined by block protect register and ends at the botto m of the flash memory array ($ffff and $3fff). when the memory is prot ected, the hven bit cannot be set in either e rase or program operations. 4.8.1 flash block protect registers each flash block protect register is implemented as an 7-bit i/o register. the bpr bit content of the regist er determines the starting location of the protected range within the flash memory. this register c ontrols the 47, 616-byte array: this register controls the 13k-byte array: address: $fe08 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 figure 4-6. 47,616-byte flash bl ock protect register (flbpr) address: $fe0b bit 7654321bit 0 read: bpr17 bpr16 bpr15 bpr14 bpr13 bpr12 bpr11 0 write: reset:00000000 figure 4-7. 13k-byt e flash block protect register 1 (flbpr1) flash memory flash block protection mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor flash memory 73 bpr[7:1] ? flash block protect bits these seven bits represent bits [ 15:9] of a 16-bit memory address. bits [8:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to t he end of flash memory, at $ffff. bpr1[7:1] ? flash bl ock protect bits these seven bits represent bits [ 15:9] of a 16-bit memory address. bits [8:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to t he end of flash memory, at $3fff. examples of block protection for 47,616-byte flash memory array: 16-bit memory address start address of flash block protect 000000000 bpr[7:1] 0 figure 4-8. flash block protect start address bpr[7:0] flash memory protected range $40 the entire 47,616 bytes of flash memory is protected . $42 ( 0100 0010 ) $4200 ( 0100 0010 0000 0000) to $ffff $44 ( 0100 0100 ) $4400 ( 0100 0100 0000 0000) to $ffff and so on... $f8 ( 1111 1000 )$f800 ( 1111 1000 0000 0000) to $ffff $fa $ffe0 to $ffff (flash vectors) $fc $ffe0 to $ffff (flash vectors) $fe $ffe0 to $ffff (flash vectors) $00?3e the entire 47,616 bytes flash memory is not protected . flash memory data sheet mc68hc908ld64 ? rev. 3.0 74 flash memory freescale semiconductor examples of block protection for 13k-byte flash memory array: bpr1[7:0] flash memory protected range $0c the entire 13k-byte flash memory is protected . $0e ( 0000 1110 ) $0e00 ( 0000 1110 0000 0000) to $3fff $10 ( 0001 0000 ) $1000 ( 0001 0000 0000 0000) to $3fff and so on... $38 ( 0011 1000 ) $3800 ( 0011 1000 0000 0000) to $3fff $3a ( 0011 1010 ) $3a00 ( 0011 1010 0000 0000) to $3fff $3c ( 0011 1100 ) $3c00 ( 0011 1100 0000 0000) to $3fff $3e ( 0011 1110 ) $3e00 ( 0011 1110 0000 0000) to $3fff $00?$0b or $40?$fe the entire 13k-byte flash memory is not protected . mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor configuration register (config) 75 data sheet ? mc68hc908ld64 section 5. configurat ion register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 5.2 introduction this section describes the config uration register , config. the configuration register enables or disables these options: stop mode recovery time (32 oscxclk cycles or 4096 oscxclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 oscxclk cycles) stop instruction computer operating pr operly module (cop) 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be wri tten once after each reset. all of the configuration register bits are clea red during reset. since the various options affect the operat ion of the mcu, it is recommended that this register be written immedi ately after reset. the conf iguration register is located at $001f. the configuration register may be read at anytime. configuration register (config) data sheet mc68hc908ld64 ? rev. 3.0 76 configuration register (config) freescale semiconductor 5.4 configuration register ssrec ? short stop recovery bit ssrec enables the cp u to exit stop mode with a delay of 32 oscxclk cycles instead of a 4096 oscxclk cycle delay. 1 = stop mode recovery after 32 os cxclk cycles 0 = stop mode recovery after 4096 oscxclk cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscillator, do not set the ssrec bit. coprs ? cop rate select bit coprs selects the cop timeout pe riod. reset clears coprs. (see section 22. computer o perating properly (cop) .) 1 = cop timeout period = 2 13 ? 2 4 oscxclk cycles 0 = cop timeout period = 2 18 ? 2 4 oscxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 22. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: 0 0 0 0 ssrec coprs stop copd write: reset:00000000 = unimplemented figure 5-1. configurat ion register (config) mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 77 data sheet ? mc68hc908ld64 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 78 central processor unit (c pu) freescale semiconductor 6.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.3 features feature of the cpu include: object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-re gister manipulation instructions 6-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressing range beyond 64-kbytes low-power stop and wait modes central processor unit (cpu) cpu registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 79 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 80 central processor unit (c pu) freescale semiconductor 6.4.2 index register the 16-bit index register allows i ndexed addressing of a 64k-byte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) central processor unit (cpu) cpu registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 81 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 82 central processor unit (c pu) freescale semiconductor 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) ar ithmetic operations. the daa in struction uses the states of the h and c fl ags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset: x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) central processor unit (cpu) cpu registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 83 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cpu registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipulation pr oduces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 84 central processor unit (c pu) freescale semiconductor c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of th e accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/logic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock. central processor unit (cpu) cpu during break interrupts mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 85 6.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock. after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if the break module is enabled, a br eak interrupt causes the cpu to execute the software inte rrupt instruction (swi) at the completion of the current cpu instruction. (see section 23. break module (brk) .) the program counter vectors to $fff c?$fffd ($fefc?$fefd in monitor mode). a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary table 6-1 provides a summary of t he m68hc08 instruction set. 6.9 opcode map the opcode map is provided in table 6-2 . central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 86 central processor unit (c pu) freescale semiconductor table 6-1. instruction se t summary (sheet 1 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) r r ? r r r imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) r r ? r r r imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) r ?? r r r dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right r ?? r r r dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c central processor unit (cpu) opcode map mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 87 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 6-1. instruction se t summary (sheet 2 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 88 central processor unit (c pu) freescale semiconductor brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction se t summary (sheet 3 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) opcode map mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 89 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? r r 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) r ?? r r r imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? r r r inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 r ?? r r ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? r r inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction se t summary (sheet 4 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 90 central processor unit (c pu) freescale semiconductor inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 r ?? r r ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? r r ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? r r ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) r ?? r r r dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right r ??0 r r dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 table 6-1. instruction se t summary (sheet 5 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) opcode map mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 91 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? r r ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) r ?? r r r dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? r r ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry r ?? r r r dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry r ?? r r r dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 table 6-1. instruction se t summary (sheet 6 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 92 central processor unit (c pu) freescale semiconductor rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) r r r r r r inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? r r ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? r r ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? r r ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction se t summary (sheet 7 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) opcode map mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor central processor unit (cpu) 93 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) r r r r r r inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? r r ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location r set or cleared n negative bit ? not affected table 6-1. instruction se t summary (sheet 8 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) data sheet mc68hc908ld64 ? rev. 3.0 94 central processor unit (cpu) freescale semiconductor table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor oscillator (osc) 95 data sheet ? mc68hc908ld64 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .96 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 97 7.4.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 97 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 97 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 97 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2 introduction the oscillator circuit is designed for use with crystals or ceramic resonators. the oscillat or circuit generates the crystal clock signal, oscxclk, at the frequency of the crystal. this signal is divided by two before being passed on to the si m for bus clock generation. figure 7-1 shows the structure of the oscillator. the oscill ator requires various external components. the mc68hc908ld64 operates from a nominal 24mhz crystal or external clock, providing an 8mhz internal bus clock. the 24mhz clock is required for various modul es, such as the cgm and usb. oscillator (osc) data sheet mc68hc908ld64 ? rev. 3.0 96 oscillator (osc) freescale semiconductor 7.3 oscillator external connections in its typical configur ation, the oscillator requires five external components. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 7-1 . this figure shows only the logical representat ion of the internal components and may not represent actual circui try. the oscillator conf iguration uses five components: crystal, x 1 (nominally 24mhz) fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (not required for 24mhz crystal) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. figure 7-1. oscillator external connections c 1 c 2 simoscen oscxclk r b x 1 r s * *r s can be zero (shorted) when used with mcu from sim 2 oscout to sim to sim osc1 osc2 higher-frequency crystals. refer to manufacturer?s data. 24mhz oscillator (osc) i/o signals mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor oscillator (osc) 97 7.4 i/o signals the following paragraphs describe the oscillator i/o signals. 7.4.1 crystal amplifi er input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. an externally generated cl ock also can feed the os c1 pin of the crystal oscillator circuit. connect the exter nal clock to the o sc1 pin and let the osc2 pin float. 7.4.2 crystal amplifi er output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 7.4.3 oscillator e nable signal (simoscen) the simoscen signal comes from the sim and enabl es the oscillator. 7.4.4 external clock source (oscxclk) oscxclk is the crystal oscillator out put signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 7-1 shows only the logical rela tion of oscxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of oscxclk is unknown and may d epend on the crystal and other external factors. also, the frequen cy and amplitude of oscxclk can be unstable at start-up. 7.4.5 oscillat or out (oscout) the clock driven to the si m is the crystal frequency divided by two. this signal is driven to the sim for genera tion of the bus clocks used by the cpu and other modules on the mcu. oscout will be divided again in the sim and results in th e internal bus frequency being one four th of the oscxclk frequency. oscillator (osc) data sheet mc68hc908ld64 ? rev. 3.0 98 oscillator (osc) freescale semiconductor 7.5 low power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 7.5.1 wait mode the wait instruction has no effect on the osci llator logic. oscxclk continues to drive to the sim module. 7.5.2 stop mode the stop instructio n disables the oscxclk output. 7.6 oscillator during break mode the oscillator continues drive oscxclk when the ch ip enters the break state. mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor clock generator module (cgm) 99 data sheet ? mc68hc908ld64 section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.5 cgm i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.1 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 103 8.5.2 pll analog power pin (vdda) . . . . . . . . . . . . . . . . . . . . . 103 8.5.3 pll analog ground pin (vssa). . . . . . . . . . . . . . . . . . . . . 103 8.5.4 crystal output frequency signal (oscxclk). . . . . . . . . . 104 8.5.5 crystal reference frequency signal (oscrclk). . . . . . . 104 8.5.6 cgm base clock output (dclk1) . . . . . . . . . . . . . . . . . . . 104 8.5.7 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 104 8.6 cgm i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 106 8.6.3 pll programming regi ster (ppg) . . . . . . . . . . . . . . . . . . . 108 8.6.4 h & v sync output control re gister (hvocr) . . . . . . . . . 110 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.9 cgm during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 112 clock generator module (cgm) data sheet mc68hc908ld64 ? rev. 3.0 100 clock generator module (cgm) freescale semiconductor 8.2 introduction this section describes the clock generator m odule (cgm). using the crystal reference clock from the o scillator module, the cgm generates the display base clock, dclk1, for the sync processor module. the cgm is able to generate a frequen cy up to 108mhz from a 24mhz reference clock. 8.3 features features of the cgm include the following: phase-locked loop with output freque ncy in integer multiples of the crystal reference programmable hardware voltage-c ontrolled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 8.4 functional description the cgm consists of th ree major sub-modules: crystal oscillator circuit which generates the buffered constant crystal frequency cl ock, oscrclk. (see section 7. oscillator (osc) .) phase-locked loop (p ll) which generates the programmable vco frequency clock cgmvclk. base clock selector ci rcuit; this software-controlled circuit selects either oscxclk divided by tw o or the vco clock cgmvclk divided by two, as the base clock dclk1. the sync processor derives other display clocks from dclk1. clock generator module (cgm) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor clock generator module (cgm) 101 figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator lock detector clock oscxclk cgmvdv simoscen oscillator (osc) interrupt control cgmint cgmrdv pll analog oscrclk osc2 osc1 select circuit v dda cgmxfc v ssa lock auto acq pllie pllf mul[7:4] reference divider vrs[7:4] (to sim) (to sim) hvocr[1:0] (from sim) cgmvclk phase-locked loop (pll) dclk1 bandwidth control (to sync processor) (see section 7. oscillator (osc) .) oscout 2 n l clock generator module (cgm) data sheet mc68hc908ld64 ? rev. 3.0 102 clock generator module (cgm) freescale semiconductor addr.register name bit 7654321bit 0 $0038 pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 $0039 pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset:00000000 $003a pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 $003f h&v sync output control register (hvocr) read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved notes: 1. when auto = 0, pllie is forced to logic zero and is read-only. 2. when auto = 0, pllf and lock read as logic zero. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[7:4] = $0, bcs is forced to logic zero and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 8-2. cgm i/o register summary table 8-1. free-running hsout, vsout, de, and dclk settings register settings output pin video modes hvocr[1:0] mul[7:4] vrs[7:4] hout frequency vout frequency dclk frequency de video mode 00 3 3 31.45khz 59.91hz 24mhz vga 640 480 01 5 3 37.87khz 60.31hz 40mhz svga 800 600 10 8 6 48.37khz 60.31hz 64mhz xga 1024 768 11 9 9 64.32khz 60.00hz 108mhz sxga 1280 1024 clock generator module (cgm) cgm i/o signals mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor clock generator module (cgm) 103 8.4.1 crystal os cillator circuit the crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. the osc1 pin is t he input to the amp lifier and the osc2 pin is the output. the simoscen si gnal from the sys tem integration module (sim) enables the cr ystal oscillator circuit. the oscxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. oscxcl k is then buffered to produce oscrclk, the pll reference clock. (see section 7. oscillator (osc) .) 8.5 cgm i/o signals the following paragraphs descr ibe the cgm i/o signals. 8.5.1 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. a small external capacitor (c f ) is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other si gnals across the c f connection. 8.5.2 pll analog power pin (vdda) vdda is the power pin used by the a nalog portions of the pll. the pin should be connected to the same voltage pot ential as the vdd pin. 8.5.3 pll analog ground pin (vssa) vssa is the ground pin us ed by the analog portions of the pll. the pin should be connected to the same voltage pot ential as the vss pin. note: route vdda and vssa carefully for maximum noise immunity and place bypass capacitors as cl ose as possible to the package. clock generator module (cgm) data sheet mc68hc908ld64 ? rev. 3.0 104 clock generator module (cgm) freescale semiconductor 8.5.4 crystal output frequency signal (oscxclk) oscxclk is the crystal oscillator out put signal. it runs at the full speed of the crystal (f xclk ) and is generated di rectly from the crystal oscillator circuit. the duty cycle of oscxc lk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of oscxclk can be unstab le at start-up. 8.5.5 crystal refer ence frequency signal (oscrclk) oscrclk is the buffered version of oscxclk. it runs at the full speed of the crystal (f xclk ) and provides the refer ence for the pll circuit. 8.5.6 cgm base clock output (dclk1) dclk1 is the clock output of the cg m. this signal goes to the sync processor, which generates the di splay clocks. dclk1 is software programmable to be eith er the oscillator output (oscxclk) or the vco clock (cgmvclk). 8.5.7 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 8.6 cgm i/o registers the following registers control and monitor operation of the cgm: pll control r egister (pctl) pll bandwidth cont rol register (pbwc) pll programming register (ppg) h & v sync output co ntrol register (hvocr) clock generator module (cgm) cgm i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor clock generator module (cgm) 105 8.6.1 pll contro l register (pctl) the pll control register contains t he interrupt enable a nd flag bits, the on/off switch, and the base clock selector bit. pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit is set also. pllf always reads as 0 when the auto bi t in the pll bandwidth control register (pbwc) is clear. the pllf bit should be cleared by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: the pllf bit shoul d not be inadvertently cl eared. any read or read- modify-write operation on the pll cont rol register clear s the pllf bit. address: $0038 bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: reset:00101111 = unimplemented figure 8-3. pll cont rol register (pctl) clock generator module (cgm) data sheet mc68hc908ld64 ? rev. 3.0 106 clock generator module (cgm) freescale semiconductor pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, dclk1 (bcs = 1). reset se ts this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit sele cts either the crystal oscillator output, oscxclk, or the vco cl ock, cgmvclk, as t he source of the cgm output, dclk1. bcs canno t be set while the pllo n bit is clear. after toggling bcs, it may take up to three oscxc lk and three cgmvclk cycles to complete the transition fr om one source clock to the other. during the transition, dclk1 is held in stas is. reset and the stop instruction clear the bcs bit. 1 = dclk1 driven by cgmvclk 0 = dclk1 driven by oscxclk note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk require s two writes to the pll control register. 8.6.2 pll bandwidth co ntrol register (pbwc) the pll bandwidth control regi ster does the following: selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode clock generator module (cgm) cgm i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor clock generator module (cgm) 107 auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. when initializing the p ll for manual operation (auto = 0), the acq bit should be cleared before turni ng the pll on. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock cgmvclk, is locked (running at the programmed frequency). when the au to bit is clear, lock reads as 0 and has no me aning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode address: $0039 bit 7654321bit 0 read: auto lock acq xld 0000 write: reset:00000000 = unimplemented figure 8-4. pll bandwidth control register (pbwc) clock generator module (cgm) data sheet mc68hc908ld64 ? rev. 3.0 108 clock generator module (cgm) freescale semiconductor xld ? crystal loss detect bit when the vco output, cgm vclk, is driving dclk1, this read/write bit indicates whether the crystal reference frequency is active or not. to check the status of the crystal reference, the following procedure should be followed: 1. write a 1 to xld. 2. wait 4 n cycles. (n is the vco freque ncy multiplier, mul[7:4].) 3. read xld. 1 = crystal refere nce is not active 0 = crystal reference is active the crystal loss detect function wor ks only when the bcs bit is set, selecting cgmvclk to drive dclk1. when bcs is clear, xld always reads as 0. bits [3:0] ? reserved for test these bits enable test functions not available in user mode. to ensure software portability fr om development systems to user applications, software should write zeros to bits [3:0] whenever writing to pbwc. 8.6.3 pll programmi ng register (ppg) the pll programming regist er contains the program ming information for the modulo feedback divider and the programming information for the hardware configurat ion of the vco. address: $003a bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 8-5. pll program ming register (ppg) clock generator module (cgm) cgm i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor clock generator module (cgm) 109 mul[7:4] ? multip lier select bits these read/write bits control the m odulo feedback divider that selects the vco frequency multiplier, n. a value of $0 in the multiplier select bits configures the m odulo feedback divider th e same as a value of $1. reset initializes these bits to $6 to give a defaul t multiply value of 6. note: the multiplier select bits have built-in protection that prevents them from being written when the p ll is on (pllon = 1). vrs[7:4] ? vco r ange select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware cent er-of-range frequency f vrs . vrs[7:4] cannot be written wh en the pllon bit in the pll control register (pctl) is set. a va lue of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. reset initializes the bits to $6 to give a default range mult iply value of 6. note: the vco range select bits have built-i n protection that prevents them from being written when the pll is on (p llon = 1) and prevents selection of the vco clo ck as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming may result in failur e of the pll to achieve lock. table 8-2. vco frequency mu ltiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 clock generator module (cgm) data sheet mc68hc908ld64 ? rev. 3.0 110 clock generator module (cgm) freescale semiconductor 8.6.4 h & v sync output control register (hvocr) the h&v sync output control register controls the pll reference input prescaler and the final free-running waveforms for the sync processor output signals on hout, vo ut, dclk, and de pins. (see section 17. sync processor .) dclkph[1:0] ? dclk output phase adjustment these two bits are programmed to adjust the dclk output phase. each increment add s approximately 2 to 3ns delay to the dclk output. hvocr[1:0] ? free runni ng video mode select bits these two bits together with mu l[7:4] and vrs[7:4] in the pll programming register determine the frequencies of the internal generated free-running si gnals for output to hout, vout, de, and dclk pins, when the sout bit is set in the syn c processor i/o control register. these two bits determine the presca ler of pll reference clock in the cgm module. when hvoc r[1:0]=11, the prescaler is 2; for other values, t he prescaler is 3. reset clears these bits, setting a default horizontal frequency of 31.25khz and a ve rtical frequency of 60hz, a video mode of 640 480. address: $003f bit 7654321bit 0 read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved figure 8-6. h&v sy nc output control register (hvocr) register settings pin outputs video modes hvocr[1:0] mul[7:4] vrs[7:4] hout frequency vout frequency dclk frequency de video mode 00 3 3 31.45khz 59.91hz 24mhz vga 640 480 01 5 3 37.87khz 60.31hz 40mhz svga 800 600 10 8 6 48.37khz 60.31hz 64mhz xga 1024 768 11 9 9 64.32khz 60.00hz 108mhz sxga 1280 1024 clock generator module (cgm) interrupts mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor clock generator module (cgm) 111 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabl ed and pllf reads as 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the vco clock cgmv clk, can be se lected as the dclk1 source by setti ng bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not fr equency-sensitive, interrupts should be disabled to prevent p ll interrupt service r outines from impeding software performance or from exceeding stack limitations. software can select cgmvclk as t he dclk1 source even if the pll is not locked (lock = 0). therefore, so ftware should make sure the pll is locked before setting the bcs bit. 8.8 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 8.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake t he mcu from wait mode also can deselect the pll output wit hout turning off the pll. clock generator module (cgm) data sheet mc68hc908ld64 ? rev. 3.0 112 clock generator module (cgm) freescale semiconductor 8.8.2 stop mode when the stop instruction execut es, the sim drives the simoscen signal low, disabling the cgm and holding low all cgm outputs (oscxclk, dclk1, and cgmint). if the stop instruction is execut ed with the vco clock, cgmvclk, driving dclk1, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the cr ystal clock, oscxclk, as the source of dclk1. when th e mcu recovers from stop, the crystal clock drives dclk1 and bcs remains clear. 8.9 cgm during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. see section 9. system integration module (sim) . to allow software to clear status bits during a break interrupt, a 1 should be written to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit durin g the break state, write a 0 to the bcfe bit. with bcfe at 0 (its def ault state), software can read and wr ite the pll control register during the break state without affecting t he pllf bit. mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 113 data sheet ? mc68hc908ld64 section 9. system integration module (sim) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 117 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.2 clock start-up from po r . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 117 9.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 119 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 9.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 121 9.4.2.3 low-voltage inhibit re set . . . . . . . . . . . . . . . . . . . . . . .121 9.4.2.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.4.2.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .122 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 122 9.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 122 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 123 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 129 9.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 129 9.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 130 system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 114 system integration module (sim) freescale semiconductor 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 134 9.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 135 9.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 136 9.2 introduction this section describes th e system integration mo dule, which supports up to 16 external and/or internal interrupts. t ogether with the cpu, the sim controls all mcu activities. a blo ck diagram of the sim is shown in figure 9-1 . figure 9-2 shows a summary of th e sim i/o registers. the sim is a system state controller that coordi nates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals: ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources system integration module (sim) introduction mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 115 figure 9-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from oscillator) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock oscxclk (from oscillator) 2 lvi reset system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 116 system integration module (sim) freescale semiconductor table 9-1 shows the internal signal na mes used in this section. addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe01 sim reset status register (srsr) read: por pin cop ilop ilad usb 0 0 write: por:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 9-2. sim i/o register summary table 9-1. signal name conventions signal name description oscxclk buffered version of osc1 from the oscillator oscout the oscxclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscxclk divided by four) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal system integration module (sim) sim bus clock control and generation mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 117 9.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, oscout, as shown in figure 9-3 . figure 9-3. osc clock signals 9.3.1 bus timing in user mode, the inte rnal bus frequency is t he oscillator frequency (oscxclk) divided by four. 9.3.2 clock start-up from por when the power-on reset module generat es a reset, t he clocks to the cpu and peripherals are inactive an d held in an inactive phase until after the 4096 oscxclk cycle por time out has comple ted. the rst is driven low by the sim du ring this entire period. the ibus clocks start upon completion of the timeout. 9.3.3 clocks in st op mode and wait mode upon exit from stop mode (by an interrupt, brea k, or reset), the sim allows oscxclk to clock the si m counter. the cpu and peripheral clocks do not become active until after the stop del ay timeout. this timeout is selectable as 4096 or 32 oscxclk cycles. (see 9.7.2 stop mode .) simoscen oscxclk from sim 2 oscout osc1 osc2 2 bus clock generators sim sim counter oscillator system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 118 system integration module (sim) freescale semiconductor in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 9.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) low-voltage inhibit (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?$ffff ($fefe?$feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 9.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register (srsr) (see 9.8 sim registers ). 9.4.1 external pin reset pulling the asynchronous rst pin low halts all pr ocessing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 os cxclk cycles, assuming th at the por was not the source of the reset (see table 9-2. pin bit set timing) . figure 9-4 shows the relative timing. table 9-2. pin bit set timing reset type number of cycles required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3) system integration module (sim) reset and system initialization mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 119 figure 9-4. extern al reset timing 9.4.2 active resets from internal sources sim module in hc08 has the capability to drive the rst pin low when internal reset events occur. all internal reset sour ces actively pull the rst pin low for 32 oscxclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be asserted for an additional 32 cycles (see figure 9- 5. internal reset timing) . an internal reset ca n be caused by an illegal address, illegal opcode, co p timeout, or por (see figure 9-6. sources of internal reset) . note that for por rese ts, the sim cycles through 4096 oscxclk cycles during whic h the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 9-5 . the cop reset is asynchro nous to the bus clock. the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. figure 9-5. inter nal reset timing figure 9-6. sources of internal reset rst iab pc vect h vect l oscout irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high oscxclk illegal address rst illegal opcode rst coprst por internal reset lvi system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 120 system integration module (sim) freescale semiconductor 9.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four osc xclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscill ator to drive oscxclk. internal clocks to the cpu and m odules are held i nactive for 4096 oscxclk cycles to allow stab ilization of t he oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 9-7. por recovery porrst osc1 oscxclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff system integration module (sim) reset and system initialization mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 121 9.4.2.2 computer operati ng properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears th e cop counter and bits 12 through 5 of the sim counter. the s im counter output, which o ccurs at least every 2 12 ? 2 4 oscxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time befor e the first timeout. the cop module is disabled if the rst pin or the irq is held at v tst while the mcu is in monitor m ode. the cop modul e can be disabled only through combinational logic conditioned with the high voltage signal on the rst pin or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. 9.4.2.3 low-voltage inhibit reset the low-voltage inhibit circuit perfo rms an internal reset when the v dd voltage falls to the lvi trip voltage v tripf . the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four oscxclk cycl es later, the cpu and memories are released from reset to allow the re set vector sequence to occur. 9.4.2.4 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. if the stop enable bit, st op, in the confi gure register (config) is logic zero, the sim treats the stop in struction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 122 system integration module (sim) freescale semiconductor 9.4.2.5 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim acti vely pulls down the rst pin for all internal reset sources. 9.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly module (cop). the sim counter overflow supplies the cl ock for the cop module. the sim counter is 12 bits long and is clo cked by the falling edge of oscxclk. 9.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. 9.5.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configure register (con fig). if the ssrec bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 oscxclk cycles down to 32 oscxclk cycles. thi s is ideal for applications using canned oscillators that do not require long st art-up times from stop mode. external crystal applications should use the full stop recovery time, that is, wi th ssrec cleared. system integration module (sim) exception control mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 123 9.5.3 sim counter and reset states external reset has no effect on the sim counter (see 9.7.2 stop mode ). the sim counter is free-running after all reset states (see 9.4.2 active resets from internal sources for counter control and internal reset recovery sequences). 9.6 exception control normally, sequential program exec ution can be c hanged in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 124 system integration module (sim) freescale semiconductor 9.6.1 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a parti cular event. figure 9-10 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 9-8 shows interrupt entry timing. figure 9-9 shows interrupt recovery timing. figure 9-8 . interrupt entry figure 9-9. interrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[15:8] pc ? 1[7:0] opcode operand i bit system integration module (sim) exception control mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 125 figure 9-10. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? usb interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 126 system integration module (sim) freescale semiconductor interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrup t may take precedence, regardless of priority, until the latched interrupt is servic ed (or the i bit is cleared). (see figure 9-10. interrupt processing .) 9.6.1.1 hardware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register), and if the corres ponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 9-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 9-11 . interrupt recognition example cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine system integration module (sim) exception control mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 127 the lda opcode is pre- fetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti pre-fetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. 9.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 9.6.2 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 9-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 128 system integration module (sim) freescale semiconductor table 9-3. interrupt sources source flag mask (1) int register flag priority (2) vector address reset none none none 0 $fffe?$ffff swi instruction none none none 0 $fffc?$fffd irq pin irqf imask if1 1 $fffa?$fffb hub start of frame soff sofie if2 2 $fff8?$fff9 hub 2nd end of frame point eof2f eof2ie hub end of packet eopf eopie hub bus signal transition detect tranf tranie hub endpoint 0 transmit txdf txdie if3 3 $fff6?$fff7 hub endpoint 0 receive rxdf rxdie device endpoint 0 transmit txd0f txd0ie if4 4 $fff4?$fff5 device endpoint 0 receive rxd0f rxd0ie usb endpoint1/2 transmit txd1f txd1ie ddc12ab alif dien if5 5 $fff2?$fff3 nakif rxif txif sclif sclien tim channel 0 ch0f ch0ie if6 6 $fff0?$fff1 tim channel 1 ch1f ch1ie if7 7 $ffee?$ffef tim overflow tof toie if8 8 $ffec?$ffed sync processor vsif vsie if9 9 $ffea?$ffeb lvsif lvsie multi-master iic mmalif mmien if10 10 $ffe8?$ffe9 mmnakif mmrxif mmtxif on-screen display dendif osdie if11 11 $ffe6?$ffe7 adc conversion complete coco aien if12 12 $ffe4?$ffe5 keyboard interrupt keyf kbi e7?kbie0 if13 13 $ffe2?$ffe3 cgm pll pllf pllie if14 14 $ffe0?$ffe1 notes : 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. 2. highest priority = 0. system integration module (sim) exception control mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 129 9.6.2.1 interrupt st atus register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present bit 1 and bit 0 ? always read 0 9.6.2.2 interrupt st atus register 2 if14?if7 ? interr upt flags 14?7 these flags indicate the presence of interrupt r equests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 9-12. interrupt st atus register 1 (int1) address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 9-13. interrupt st atus register 2 (int2) system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 130 system integration module (sim) freescale semiconductor 9.6.3 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 9.6.4 break interrupts the break module can st op normal program flow at a software- programmable break point by asserti ng its break interrupt output (see section 23. break module (brk) ). the sim puts t he cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 9.6.5 status flag pr otection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in t he sim break flag contro l register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing st atus flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step cleari ng mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. system integration module (sim) low-power modes mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 131 9.7 low-power modes executing the wait or stop instruction puts t he mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 9.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 9-14 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in configuration register (config) is logic ze ro, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 9-14. wait mode entry timing figure 9-15 and figure 9-16 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 132 system integration module (sim) freescale semiconductor figure 9-15. wait recovery from interrupt or break figure 9-16. wait recover y from internal reset 9.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the oscillator si gnals (oscout and oscxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in configuration register (config). if ssrec is set, stop recovery is reduced from the nor mal delay of 4096 oscxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require lo ng start-up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 oscxclk 32 cycles 32 cycles system integration module (sim) low-power modes mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 133 a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the sim break st atus register (sbsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 9-17 shows stop mode entry timing. figure 9-17. stop mode entry timing figure 9-18. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. oscxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 134 system integration module (sim) freescale semiconductor 9.8 sim registers the sim has three memo ry mapped registers. table 9-4 shows the mapping of thes e registers. 9.8.1 sim break stat us register (sbsr) the sim break status register contains a flag to indica te that a break caused an exit from st op or wait mode. sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. table 9-4. sim registers summary address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r= reserved figure 9-19. sim break stat us register (sbsr) system integration module (sim) sim registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor system integration module (sim) 135 9.8.2 sim reset st atus register (srsr) this register contains six flags that show the sour ce of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clear s all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad usb 0 0 write: por:10000000 = unimplemented figure 9-20. sim reset status register (srsr) system integration module (sim) data sheet mc68hc908ld64 ? rev. 3.0 136 system integration module (sim) freescale semiconductor cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr usb ? universal serial bus reset bit 1 = last reset caused by an usb module 0 = por or read of srsr 9.8.3 sim break flag co ntrol register (sbfcr) the sim break flag control r egister contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 9-21. sim break flag c ontrol register (sbfcr) mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor monitor rom (mon) 137 data sheet ? mc68hc908ld64 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single-wir e interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements fo r in-circuit programming. monitor rom (mon) data sheet mc68hc908ld64 ? rev. 3.0 138 monitor rom (mon) freescale semiconductor 10.3 features features of the mo nitor rom include: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory progr amming interface 1024 bytes monitor rom code size ($fa00 to $fdff) monitor mode entry wi thout high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute c ode downloaded into ram by a host computer while most mcu pins reta in normal operating mode functions. all communication between the host computer and t he mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and require s a pull-up resistor. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. monitor rom (mon) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor monitor rom (mon) 139 figure 10-1. moni tor mode circuit + + + + 10 m ? x1 v dd mc145407 mc74lcx125 68hc908ld64 rst irq osc1 osc2 v ss1 v dd 1 pta0 v dd 10 k ? 0.1 f 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 9.8304 mhz 10 k ? ptc3 v dd 10 k ? b a (see notes) 5 6 ptc0 ptc1 v dd 10 k ? v ss2 v dd 2 v ssa v dd a 0.1 f v dd dplus0 dminus0 ptd4/ddcscl ptd5/ddcsda pta7 v tst 10 ? d c (see notes) sw2 sw1 notes: 1. sw2: position c ? for monitor mode entry when irq = v tst : sw1: position a ? bus clock = oscxclk 4 sw1: position b ? bus clock = oscxclk 2 2. sw2: position d ? for monitor mode entry when reset vector is blank ($fffe and $ffff = $ff): bus clock = oscxclk 4; ptc0, ptc1, and ptc3 voltages are not required. 3. see table 24-4 for irq voltage level requirements. monitor rom (mon) data sheet mc68hc908ld64 ? rev. 3.0 140 monitor rom (mon) freescale semiconductor 10.4.1 entering monitor mode table 10-1 shows the pin conditions fo r entering monitor mode. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communi cation at 9600 baud provided one of the following sets of conditions is met: 1. if monitor entry is by high voltage on irq (irq = v tst ) ? the external clock is 4. 9152 mhz with pt c3 low or 9.8304 mhz with ptc3 high 2. if monitor entry is by blank reset vect or ($fffe and $ffff both contain $ff; erased state): ? the external clock is 9.8304 mhz note: holding the ptc3 pin low when ente ring monitor mode by a high voltage causes a bypass of a divide-by-two stage at the oscillator. the oscout frequency is equal to the oscxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. note: if the reset vector is blank and moni tor mode is entered, the chip will see an additional reset cycle after the init ial por reset. once the part has been programmed, the traditi onal method of applyi ng a high voltage, v tst , to irq must be used to enter monitor mode. enter monitor mode with the pin configuration shown in table 10-1 after a reset. the rising edge of reset la tches monitor mode. once monitor mode is latched, the values on the specif ied pins can change. once out of reset, t he mcu monitor mode firmwa re then sends a break signal (10 consecutive logi c zeros) to the host co mputer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow t he host to determine t he necessary baud rate. mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor monitor rom (mon) 141 monitor rom (mon) functional description table 10-1. monitor mode si gnal requirement s and options irq rst address $fffe/ $ffff ptc3 ptc1 ptc0 pta7 (1) dplus0 dminus0 ptd4 ptd5 external clock (2) bus frequency cop baud rate comment xgndx xxxx x x 0disabled0no operation until reset goes high. v tst v dd or v tst x 0010 0 4. 9152 mhz 2.4576 mhz disabled 9600 enters monitor mode. ptc0, ptc1, and ptc3 voltages only required if irq = v tst ; ptc3 determines frequency divider. exit monitor mode by por or by rst low then high v tst v dd or v tst x 1010 0 9. 8304 mhz 2.4576 mhz disabled 9600 enters monitor mode. ptc0, ptc1, and ptc3 voltages only required if irq = v tst ; ptc3 determines frequency divider. exit monitor mode by por or by rst low then high v dd or gnd v dd blank "$ffff" x x x 0 0 9.8304 mhz 2.4576 mhz disabled 9600 enters monitor mode. external frequency always divided by 4. exit monitor mode by por only. v dd or gnd v dd not blankxxxx x x ?enabled?enters user mode. notes : 1. pta7 = 0 if serial communication; pta7 = 1 if parallel communication 2. external clock is derived by a 4.9152/9 .8304 mhz crystal or off-chip oscillator monitor rom (mon) data sheet mc68hc908ld64 ? rev. 3.0 142 monitor rom (mon) freescale semiconductor monitor mode uses differ ent vectors for reset and swi. the alternate vectors are in the $fe page in stead of the $ff page and allow code execution from the internal monito r firmware instead of user code. when the host computer has comple ted downloading code into the mcu ram, this code can be executed by driving pta0 low while asserting rst low and then high. the internal monitor rom fi rmware will interpret the low on pta0 as an i ndication to jump to ra m, and execution control will then continue from ram. execution of an swi from the downloaded code will return program control to the internal monitor rom firmware. alternatively, the host can send a run command, whic h executes an rti, and this can be used to send control to the addr ess on the stack pointer. the cop module is disabled in monitor mode as long as v tst is applied to the irq or the rst pin. (see section 9. system integration module (sim) for more information on modes of operation.) table 10-2 is a summary of the differ ences between user mode and monitor mode. 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-2 and figure 10-3 .) table 10-2. mode differences modes functions cop reset vector high reset vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd monitor disabled (1) notes : 1. if the high voltage (v tst ) is removed from the irq pin, the sim asserts its cop enable output. the cop is an option enabled or disa bled by the copd bit in the configuration register. $fefe $feff $fefc $fefd monitor rom (mon) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor monitor rom (mon) 143 figure 10-2. moni tor data format figure 10-3. sample monitor waveforms the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. 10.4.3 echoing as shown in figure 10-4 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. figure 10-4. read transaction any result of a command appears after the ec ho of the last byte of the command. 10.4.4 break signal a start bit followed by ni ne low bits is a break signal (see figure 10-5). when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 stop bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result monitor rom (mon) data sheet mc68hc908ld64 ? rev. 3.0 144 monitor rom (mon) freescale semiconductor figure 10-5. break transaction 10.4.5 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo table 10-3. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence read read echo sent to monitor address high address high address low data return address low monitor rom (mon) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor monitor rom (mon) 145 table 10-4. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence table 10-5. iread (i ndexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo sent to monitor address high address high address low address low data data iread iread echo sent to monitor data return data monitor rom (mon) data sheet mc68hc908ld64 ? rev. 3.0 146 monitor rom (mon) freescale semiconductor a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64k-byte memory map. table 10-6. iwrite (i ndexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence table 10-7. read sp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence iwrite iwrite echo sent to monitor data data readsp readsp echo sent to monitor sp return sp high low monitor rom (mon) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor monitor rom (mon) 147 10.4.6 baud rate the communication baud rate is cont rolled by crystal frequency and the state of the ptc3 pin upon entry into monitor mode. when ptc3 is high, the divide by ratio is 1024. if the ptc3 pin is at logic zero upon entry into monitor mode, the divi de by ratio is 512. table 10-8. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 10-9. monitor baud rate selection crystal frequency ptc3 pin baud rate 9.8304 mhz 0 19200 bps 9.8304 mhz 1 9600 bps monitor rom (mon) data sheet mc68hc908ld64 ? rev. 3.0 148 monitor rom (mon) freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 149 data sheet ? mc68hc908ld64 section 11. timer interface module (tim) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 154 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .155 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 155 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 156 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 157 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 161 11.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 163 11.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 164 11.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 165 11.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 168 timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 150 timer interface module (tim) freescale semiconductor 11.2 introduction this section describes the timer inte rface module (tim2, version b). the tim is a two-channel time r that provides a timi ng reference with input capture, output compare, and pul se-width-modulation functions. figure 11-1 is a block diagram of the tim. 11.3 features features of the tim include the following: two input capture/ou tput compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? seven-frequency internal bus clock prescaler selection free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits note: tch1 (timer channel 1) is not bonded to an external pin on this mcu. therefore, any references to the ti mer tch1 pin in the following text should be interpreted as not available ? but the inter nal status and control registers ar e still available. 11.4 pin name conventions the tim shares the tch0 pin with the sync processor clamp output. table 11-1. pin name conventions tim generic pin name: tch0 full tim pin name: clamp/tch0 pin selected for tch0 by: els0b:els0a timer interface module (tim) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 151 11.5 functional description figure 11-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels are program mable independently as input capture or output compare channels. figure 11-1. tim block diagram tch1 tch0 (not available) prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a interrupt logic port logic interrupt logic interrupt logic port logic timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 152 timer interface module (tim) freescale semiconductor addr.register name bit 7654321bit 0 $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 timer interface module (tim) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 153 11.5.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rate s from the internal bus clock. the prescaler select bits, ps[2:0], in t he tim status and control register (tsc) select the tim clock source. 11.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 11.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset = unimplemented addr.register name bit 7654321bit 0 timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 154 timer interface module (tim) freescale semiconductor 11.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow perio d. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. timer interface module (tim) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 155 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enabl es the tim channel 1 registers to synchronously control t he output after the tim overflows. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the output are the ones writte n to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 11.5.4 pulse widt h modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-2 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic one. program the tim to set the pin if the state of the pwm pulse is logic zero. timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 156 timer interface module (tim) freescale semiconductor figure 11-2. pwm peri od and pulse width the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is 000 (see 11.10.1 tim status and control register (tsc) ). the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface module (tim) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 157 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger val ue in an output compare interrupt routine (at the end of the current pulse) c ould cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel re gisters of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writ ing to the tim channel 1 registers enables the ti m channel 1 registers to synchronously control the pulse width at t he beginning of the nex t pwm period. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the pulse width are the ones written to last. tsc0 c ontrols and monitors the buffered pwm functi on, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 158 timer interface module (tim) freescale semiconductor note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. user so ftware should track the currently active channel to prevent writing a new value to the active channel. writing to the active c hannel registers is the same as generating unbuffer ed pwm signals. 11.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter and pre scaler by setting the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 11-3 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-3 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop. timer interface module (tim) interrupts mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 159 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output.tim channel 0 status and control register (tsc0) controls and monito rs the pwm signal from the linked channels. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 11.10.4 tim channel status and control registers (tsc0:tsc1) . 11.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overfl ow interrupt enable bit, toie, enables tim overflow cpu interr upt requests. tof and toie are in the tim status and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxie=1. chxf and chxie ar e in the tim channel x status and control register. 11.7 low-power modes the wait and stop in structions puts the mcu in low-power- consumption standby modes. 11.7.1 wait mode the tim remains active after the executi on of a wait instru ction. in wait mode the tima register s are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 160 timer interface module (tim) freescale semiconductor 11.7.2 stop mode the tim is inactive after the executi on of a stop instru ction. the stop instruction does no t affect register conditions or the state of the tim counter. tim operation resumes when the mcu ex it stop mode after an external interrupt. 11.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the break flag control regi ster (bfcr) enables software to clear status bits during the break state. (see 23.6.4 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 11.9 i/o signals the tim channel i/o pin is clamp/ tch0. the pin is shared with sync processor clamp output signal. tch0 pin is programmable independently as an input capture pin or an output compare pin. it also can be configur ed as a buffered output compare or buffered pwm pin. timer interface module (tim) i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 161 11.10 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0 and tsc1) tim channel registers (tch 0h:tch0l and tch1h:tch1l) 11.10.1 tim status and co ntrol register (tsc) the tim status and control r egister does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when t he tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register w hen tof is set and then writing a logic zero to tof. if anot her tim overflow oc curs before the clearing sequence is complete, then wr iting logic zero to tof has no address: $000a bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 11-3. tim st atus and control register (tsc) timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 162 timer interface module (tim) freescale semiconductor effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is rese t and always reads as l ogic zero. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the tclk pin or one of the seven prescaler outputs as the i nput to the tim counter as table 11-2 shows. reset clears the ps[2:0] bits. timer interface module (tim) i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 163 11.10.2 tim counter r egisters (tcnth:tcntl) the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. table 11-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 not available address: $000c tcnth bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 address: $000d tcntl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 = unimplemented figure 11-4. tim counter registers (tcnth:tcntl) timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 164 timer interface module (tim) freescale semiconductor note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. 11.10.3 tim counter modul o registers (tmodh:tmodl) the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow inte rrupts until the low byte (tmodl) is written. reset sets the ti m counter modulo registers. note: reset the tim counter bef ore writing to the tim counter modulo registers. address: $000e tmodh bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 address: $000f tmodl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 11-5. tim counter modu lo registers (tmodh:tmodl) timer interface module (tim) i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 165 11.10.4 tim channel st atus and control r egisters (tsc0:tsc1) each of the tim channel status and control regi sters does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 0% and 1 00% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is address: $0010 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0013 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-6. tim channel status and control registers (tsc0:tsc1) timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 166 timer interface module (tim) freescale semiconductor an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests are enabled (chxie=1), clear chxf by reading the tim channel x status an d control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset cl ears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 0:0, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 0:0, this read/write bit selects the initial output level of the tchx pin. (see table 11-3 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high timer interface module (tim) i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 167 note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when els0b and els0a are both cl ear, channel 0 is not connected to the clamp/tch0 pin. the pin is available as the clamp output of the sync processor. table 11-3 shows how elsxb and elsx a work. reset clears the elsxb and elsxa bits. note: before enabling a tim ch annel register for input capture operation, make sure that the tchx pin is st able for at leas t two bus clocks. table 11-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin is clamp of sync processor (1) ; initial output level high notes : 1. for clamp/tch0 pin only. x1 0 0 pin is clamp of sync processor (1) ; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 168 timer interface module (tim) freescale semiconductor tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not t oggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic one, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 11-7 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 11-7. chxmax latency 11.10.5 tim channel regi sters (tch0h/l:tch1h/l) these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module (tim) i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor timer interface module (tim) 169 in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. address: $0011 tch0h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0012 tch0l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset address: $0014 tch1h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0015 tch1l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset figure 11-8. tim channel regi sters (tch0h/l:tch1h/l) timer interface module (tim) data sheet mc68hc908ld64 ? rev. 3.0 170 timer interface module (tim) freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor pulse width modulator (pwm) 171 data sheet ? mc68hc908ld64 section 12. pulse width modulator (pwm) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 12.4 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.4.1 pwm data registers 0 to 7 (0 pwm?7pwm). . . . . . . . . . . 173 12.4.2 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . . 174 12.2 introduction eight 8-bit pwm channels are av ailable on the mc68hc908ld64. channels 0 to 7 are shared with port- b i/o pins under t he control of the pwm control register. 12.3 functional description each 8-bit pwm channel is composed of an 8-bit register which contains a 5-bit pwm in m sb portion and a 3-bit binary rate multiplier (brm) in lsb portion. there are eight pwm data registers, controlling each pwm channel. the value program med in the 5-bit pwm portion will determine the pulse length of t he output. the clock to the 5-bit pwm portion is the system bus clock, the r epetition rate of the out put is hence 187.5khz at 6mhz clock. the 3-bit brm will generate a number of narro w pulses which are equally distributed among an 8-pwm-cy cle frame. the number of pulses generated is equal to the number program med in the 3-bit brm portion. example of the waveforms are shown in figure 12-4 . pulse width modulator (pwm) data sheet mc68hc908ld64 ? rev. 3.0 172 pulse width modulator (pwm) freescale semiconductor combining the 5-bit pwm together wit h the 3-bit brm, the average duty cycle at the output will be (m+n/8)/32, where m is the cont ent of the 5-bit pwm portion, and n is t he content of the 3-bit brm portion. using this mechanism, a true 8-bit resolution pwm type dac with reasonably high repetition rate can be obtained. the value of each pwm data register is continuously com pared with the content of an internal counter to determine the state of each pwm channel output pin. double buffering is not used in this pwm design. addr.register name bit 7654321bit 0 $0070 pwm0 data register (0pwm) read: 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 write: $0071 pwm1 data register (1pwm) read: 1pwm4 1pwm3 1pwm2 1pwm1 1pwm0 1brm2 1brm1 1brm0 write: $0072 pwm2 data register (2pwm) read: 2pwm4 2pwm3 2pwm2 2pwm1 2pwm0 2brm2 2brm1 2brm0 write: $0073 pwm3 data register (3pwm) read: 3pwm4 3pwm3 3pwm2 3pwm1 3pwm0 3brm2 3brm1 3brm0 write: $0074 pwm4 data register (4pwm) read: 4pwm4 4pwm3 4pwm2 4pwm1 4pwm0 4brm2 4brm1 4brm0 write: $0075 pwm5 data register (5pwm) read: 5pwm4 5pwm3 5pwm2 5pwm1 5pwm0 5brm2 5brm1 5brm0 write: $0076 pwm6 data register (6pwm) read: 6pwm4 6pwm3 6pwm2 6pwm1 6pwm0 6brm2 6brm1 6brm0 write: $0077 pwm7 data register (7pwm) read: 7pwm4 7pwm3 7pwm2 7pwm1 7pwm0 7brm2 7brm1 7brm0 write: $0078 pwm control register (pwmcr) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 figure 12-1. pwm i/o register summary pulse width modulator (pwm) pwm registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor pulse width modulator (pwm) 173 12.4 pwm registers the pwm module uses of nine registers for data and control functions. pwm data registers ($0070?$0077) pwm control r egister ($0078) 12.4.1 pwm data regist ers 0 to 7 (0pwm?7pwm) the output waveform of the eight pw m channels are each configured by an 8-bit register, which contains a 5-bit pwm in msb portion and a 3-bit binary rate multiplier (brm) in lsb portion xpwm4?xpwm0 ? pwm bits the value programmed in the 5-bi t pwm portion will determine the pulse length of t he output. the clock to the 5-bit pwm portion is the system bus clock, the repetition rate of the output is hence f op 32. examples of pwm output waveforms are shown in figure 12-4 . xbrm2?xbrm0 ? binary rate multiplier bits the 3-bit brm will generate a number of narro w pulses which are equally distributed am ong an 8-pwm-cycle fr ame. the number of pulses generated is equal to the number progr ammed in the 3-bit brm portion. examples of pwm ou tput waveforms are shown in figure 12-4 . address: $0070?$0077 bit 7654321bit 0 read: xpwm4 xpwm3 xpwm2 xpwm1 xpwm0 xbrm2 xbrm1 xbrm0 write: reset:00000000 figure 12-2. pwm data regi sters 0 to 7 (0pwm?7pwm) pulse width modulator (pwm) data sheet mc68hc908ld64 ? rev. 3.0 174 pulse width modulator (pwm) freescale semiconductor 12.4.2 pwm control register (pwmcr) pwm7e?pwm0e ? pwm output enable setting a bit to 1 will enable th e corresponding pwm channel to use as pwm output. a zero configures the corresponding pwm pin as a standard i/o port pin. re set clears these bits. 1 = port pin configured as pwm output 0 = port pin configured as standard i/o port pin. address: $0078 bit 7654321bit 0 read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 figure 12-3. pwm cont rol register (pwmcr) table 12-1. pwm channel s and port i/o pins port pin pwm channel control bit ptb0 pwm0 pwm0e ptb1 pwm1 pwm1e ptb2 pwm2 pwm2e ptb3 pwm3 pwm3e ptb4 pwm4 pwm4e ptb5 pwm5 pwm5e ptb6 pwm6 pwm6e ptb7 pwm7 pwm7e pulse width modulator (pwm) pwm registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor pulse width modulator (pwm) 175 figure 12-4. 8-bit pwm output waveforms m=$00 1 pwm cycle = 32t m=$01 m=$0f m=$1f t=1 cpu clock period (0.167ms if cpu clock=6mhz) pulse inserted at end of pwm cycle n pwm cycles where pulses are inserted in a 8-cycle frame number of inserted pulses in a 8-cycle frame xx1 4 1 x1x 2, 6 2 1xx 1, 3, 5, 7 4 31t 16t 16t 31t t m = value set in 5-bit pwm (bit3-bit7) n = value set in 3-bit brm (bit0-bit2) t depends on setting of n. pulse width modulator (pwm) data sheet mc68hc908ld64 ? rev. 3.0 176 pulse width modulator (pwm) freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor analog-to-digital converter (adc) 177 data sheet ? mc68hc908ld64 section 13. analog-to-digital converter (adc) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 13.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 13.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7.1 adc analog power pin (vdda). . . . . . . . . . . . . . . . . . . . . 182 13.7.2 adc analog ground pin (vssa) . . . . . . . . . . . . . . . . . . . .182 13.7.3 adc voltage reference high pin (v rh) . . . . . . . . . . . . . . 182 13.7.4 adc voltage reference low pin ( vrl). . . . . . . . . . . . . . . 182 13.7.5 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .183 13.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 185 analog-to-digital converter (adc) data sheet mc68hc908ld64 ? rev. 3.0 178 analog-to-digital converter (adc) freescale semiconductor 13.2 introduction this section describes the analog-to-digital converter (adc). the adc is a 6-channel 8-bit succe ssive approximation adc. 13.3 features features of the ad c module include: six channels with multiplexed input linear successive approximation 8-bit resolution single or cont inuous conversion conversion complete flag or conversion complete interrupt addr.register name bit 7654321bit 0 $003b adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003c adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $003d adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 13-1. adc i/o register summary analog-to-digital converter (adc) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor analog-to-digital converter (adc) 179 13.4 functional description six adc channels are avail able for sampling exter nal sources at pins ptc5?ptc0. an analog multiplexer al lows the single adc converter to select one of the six adc channels as adc vo ltage input (adcvin). adcvin is converted by the successi ve approximation register-based counters. the adc resolu tion is eight bits. when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 13-2 shows a block diagram of the adc. figure 13-2. adc block diagram internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock adch[4:0] adc data register adiv[2:0] aien coco disable disable adc channel x read ddrc write ddrc reset write ptc read ptc ptcx/adcx ddrcx ptcx (1 of 6 channels) analog-to-digital converter (adc) data sheet mc68hc908ld64 ? rev. 3.0 180 analog-to-digital converter (adc) freescale semiconductor 13.4.1 adc port i/o pins ptc5/adc5?ptc0/adc0 are general-pur pose i/o pins that are shared with the adc channels. th e channel select bits, adch[4:0], in the adc status and control regist er define which adc ch annel/port pin will be used as the input signal. the adc overri des the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and c an be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the ad c. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. 13.4.2 voltage conversion when the input voltage to the adc equals to vrh, the adc converts the signal to $ff (full scale ). if the input volt age equals to vrl, the adc converts it to $00. input voltages between vrh a nd vrl is a straight-line linear conversion. all other input volta ges will result in $ff if greater than vrh and $00 if less than vrl. note: input voltage should not exceed the analog supply voltages. 13.4.3 conversion time sixteen adc internal cl ocks are required to perfo rm one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a wr ite to the adscr. if the adc internal clock is selected to run at 1mhz, then one conversion will take 16 s to complete. with a 1mhz adc internal clock t he maximum sample rate is 62.5khz. 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conversion time bus frequency analog-to-digital converter (adc) interrupts mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor analog-to-digital converter (adc) 181 13.4.4 continuous conversion in the continuous conv ersion mode, the adc cont inuously converts the selected channel filling t he adc data register wi th new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not . conversions will continue until the adco bit is clear ed. the conversion complete bit, coco, in the adc status and control register is set after each conversion and can be cleared by writing to the adc status and control regi ster or reading of the adc data register. 13.4.5 accuracy and precision the conversion process is monot onic and has no missing codes. 13.5 interrupts when the aien bit is se t, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. the interr upt vector is defined in table 2-1 . v ector addresses . 13.6 low-power modes the wait and stop in struction can put th e mcu in low-power consumption standby modes. 13.6.1 wait mode the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by se tting the adch[4:0] bits in the adc status and control register to l ogic 1?s before executi ng the wait instruction. analog-to-digital converter (adc) data sheet mc68hc908ld64 ? rev. 3.0 182 analog-to-digital converter (adc) freescale semiconductor 13.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conver sions resume when the mcu exits stop mode. allow one conver sion cycle to stabilize the analog circuitry before attempting a new adc conversion af ter exiting stop mode. 13.7 i/o signals the adc module has six channels that are shared with port c i/o pins, ptc5/adc5?ptc0/adc0. 13.7.1 adc analog power pin (vdda) the adc analog portion uses vdda as its power pin. connect the vdda pin to the same vo ltage potential as vdd. external filtering may be necessary to ensure cl ean vdda for good results. note: route vdda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 13.7.2 adc analog ground pin (vssa) the adc analog portion uses vssa as its gr ound pin. connect the vssa pin to the same vo ltage potential as vss. 13.7.3 adc voltage re ference high pin (vrh) vrh is the high voltage reference for the adc. 13.7.4 adc voltage re ference low pin (vrl) vrl is the low voltage reference for the adc. 13.7.5 adc volt age in (adcvin) adcvin is the input volt age signal from one of the six adc channels to the adc module. analog-to-digital converter (adc) i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor analog-to-digital converter (adc) 183 13.8 i/o registers three i/o registers control and monitor adc operation: adc status and cont rol register (adscr) adc data register (adr) adc input clock register (adiclk) 13.8.1 adc status and control register function of the adc stat us and control register is described here. coco ? conversions complete bit when the aien bit is a l ogic 0, the coco is a read-only bit which is set each time a conversion is comple ted. this bit is cleared whenever the adc status and contro l register is written, or whenever the adc data register is read. reset clears this bit. when the aien bit is a logic 1 (cpu interrupt enabled), the coco is a read-only bit, and will always be lo gic 0 when read. 1 = conversion completed (aien = 0) 0 = conversion not co mpleted (aien = 0) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status and c ontrol register is writ ten. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $003b bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 13-3. adc status and contro l register (adscr) analog-to-digital converter (adc) data sheet mc68hc908ld64 ? rev. 3.0 184 analog-to-digital converter (adc) freescale semiconductor adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels or reference voltages. th e five channel select bits are detailed in the table 13-1 . note: care should be taken when using a port pin as both an analog and a digital input simultaneous ly to prevent switchin g noise from corrupting the analog signal. note: recovery from the disabled stat e requires one conversion cycle to stabilize. table 13-1. mux channel select adch4 adch3 adch2 ad ch1 adch0 adc channel input select 00000 adc0 ptc0/adc0 00001 adc1 ptc1/adc1 00010 adc2 ptc2/adc2 00011 adc3 ptc3/adc3 00100 adc4 ptc4/adc4 00101 adc5 ptc5/adc5 00110 unused (1) ? 11010 11011 ? reserved 11 1 0 0 ? unused 11 1 0 1 vrh 11 1 1 0 vrl 11 1 1 1 adc power off notes : 1. if any unused channels are selected, the resulting adc conversion will be unknown. analog-to-digital converter (adc) i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor analog-to-digital converter (adc) 185 13.8.2 adc data register one 8-bit result regist er, adc data register (a dr), is provided. this register is updated each time an adc conversion completes. 13.8.3 adc input clock register the adc input clock register (adiclk) select s the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv[2:0] form a 3-bit field which selects the divide ratio used by the adc to generate the in ternal adc clock. table 13-2 shows the available clock configurations. the adc clock shou ld be set to approximately 1mhz. address: $003c bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 13-4. adc data register (adr) address: $003d bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 13-5. adc input cl ock register (adiclk) analog-to-digital converter (adc) data sheet mc68hc908ld64 ? rev. 3.0 186 analog-to-digital converter (adc) freescale semiconductor table 13-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 187 data sheet ? mc68hc908ld64 section 14. universal serial bus module (usb) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 14.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 14.5 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 14.6 hub function i/o r egisters . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.6.1 usb hub root port control r egister (hrpcr) . . . . . . . . . 194 14.6.2 usb hub downstream port control registers (hdp1cr?hdp4cr) . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.6.3 usb sie timing interr upt register (sietir) . . . . . . . . . . . 198 14.6.4 usb sie timing stat us register (sietsr) . . . . . . . . . . . . 200 14.6.5 usb hub address regi ster (haddr) . . . . . . . . . . . . . . . . 202 14.6.6 usb hub interrupt r egister 0 (hir0) . . . . . . . . . . . . . . . . . 203 14.6.7 usb hub control regi ster 0 (hcr0) . . . . . . . . . . . . . . . . . 205 14.6.8 usb hub endpoint 1 control and data register (hcdr) . 206 14.6.9 usb hub status regist er (hsr) . . . . . . . . . . . . . . . . . . . . 208 14.6.10 usb hub endpoint 0 data r egisters (he0d0?he0d7). . . 209 14.7 embedded device function i/o registers . . . . . . . . . . . . . . . 209 14.7.1 usb embedded devi ce address register (daddr). . . . . 210 14.7.2 usb embedded device interrupt register 0 (dir0) . . . . . 210 14.7.3 usb embedded device interrupt register 1 (dir1) . . . . . 212 14.7.4 usb embedded device control register 0 (dcr0) . . . . . 213 14.7.5 usb embedded device control register 1 (dcr1) . . . . . 215 14.7.6 usb embedded device control register 2 (dcr2) . . . . . 216 14.7.7 usb embedded device status register (dsr ) . . . . . . . . . 217 14.7.8 usb embedded device e ndpoint 0 data registers (de0d0?de0d7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.7.9 usb embedded device e ndpoint 1/2 data registers (de1d0?de1d7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 188 universal serial bus module (usb) freescale semiconductor 14.2 introduction this section describes the universa l serial bus (usb) module. this mc68hc908ld64?s usb m odule supports both embedded full-speed device and hub functions with one upstream port and four downstream ports. 14.3 features features of the usb modul e include the following: integrated usb transceiver supporting both full-speed and low-speed functions usb data control logic ? packet decoding/generation ? crc generation and checking ? nrzi encoding/decoding ? bit-stuffing usb reset support suspend and resume operations remote wakeup support stall, nak, and a ck handshake generation features of the hub functi on include the following: hub control endpoint 0 ? 8-byte transmit buffer ? 8-byte receive buffer hub interrupt endpoint 1 ? 1-byte transmit buffer usb interrupts ? transaction interrupt driven ? start of frame interrupt universal serial bus module (usb) i/o pins mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 189 ? eof2 interrupt ? end of packet interrupt ? signal transition interrupt ? frame timer locked interrupt hub repeater and controller function ? downstream and upst ream connectivity ? bus state evaluation ? selective reset, suspend and resume ? fault condition ha rdware detection features of the embedded device f unction include the following: device control endpoint 0 ? 8-byte transmit buffer ? 8-byte receive buffer device interrupt endpoints 1 and 2 ? 8-byte transmit buffer usb generated interrupts ? transaction interrupt driven 14.4 i/o pins the usb module uses ten i/o pin (five pairs), with two dedicated pins for the upstream port pair and eight shar ed port i/o pins for the downstream ports. the full name of the usb i/o pins are listed in table 14-1 . the generic pin name appear in t he text that follows. universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 190 universal serial bus module (usb) freescale semiconductor table 14-1. usb i/o pins usb generic pin names: full mcu pin names: pin selected for usb function by: d0+ dplus0 ? d0? dminus0 d1+ pte0/dplus1 usbds1e bit in pecr ($0068) d1? pte1/dminus1 d2+ pte2/dplus2 usbds2e bit in pecr ($0068) d2? pte3/dminus2 d3+ pte4/dplus3 usbds3e bit in pecr ($0068) d3? pte5/dminus3 d4+ pte6/dplus4 usbds4e bit in pecr ($0068) d4? pte7/dminus4 addr.register name bit 7654321bit 0 $0020 to $0027 usb embedded device endpoint 0 data register 0 to 7 (de0d0 to de0d7) read: de0rx7 de0rx6 de0rx5 de0r x4 de0rx3 de0rx2 de0rx1 de0rx0 write: de0tx7 de0tx6 de0tx5 de0tx4 de0tx3 de0tx2 de0tx1 de0tx0 reset: indeterminate after reset $0028 to $002f usb embedded device endpoint 1/2 data register 0 to 7 (de1d0 to de1d7) read: write: de1tx7 de1tx6 de1tx5 de1tx4 de1tx3 de1tx2 de1tx1 de1tx0 reset: indeterminate after reset $0030 to $0037 usb hub endpoint 0 data register 0 to 7 (he0d0 to he0d7) read: he0rx7 he0rx6 he0rx5 he0r x4 he0rx3 he0rx2 he0rx1 he0rx0 write: he0tx7 he0tx6 he0tx5 he0tx4 he0tx3 he0tx2 he0tx1 he0tx0 reset: indeterminate after reset $0047 usb embedded device control register 2 (dcr2) read: 0000 enable2 enable1 dstall2 dstall1 write: reset:00000000 $0048 usb embedded device address register (daddr) read: deven dadd6 dadd5 dadd4 dadd3 dadd2 dadd1 dadd0 write: reset:00000000 x = indeterminate = unimplemented figure 14-1. usb i/ o register summary universal serial bus module (usb) i/o pins mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 191 $0049 usb embedded device interrupt register 0 (dir0) read: txd0f rxd0f 0 0 txd0ie rxd0ie 00 write: txd0fr rxd0fr reset:00000000 $004a usb embedded device interrupt register 1 (dir1) read: txd1f 0 0 0 txd1ie 000 write: txd1fr reset:00000000 $004b usb embedded device control register 0 (dcr0) read: t0seq dstall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $004c usb embedded device control register 1 (dcr1) read: t1seq endadd tx1e 0 tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $004d usb embedded device status register (dsr) read: drseq dsetup dtx1st 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: dtx1str reset:00000000 $0051 usb hub downstream port 1 control register (hdp1cr) read: pen1 lowsp1 rst1 resum1 susp1 0d1+d1? write: reset:000000xx $0052 usb hub downstream port 2 control register (hdp2cr) read: pen2 lowsp2 rst2 resum2 susp2 0d2+d2? write: reset:000000xx $0053 usb hub downstream port 3 control register (hdp3cr) read: pen3 lowsp3 rst3 resum3 susp3 0d3+d3? write: reset:000000xx $0054 usb hub downstream port 4 control register (hdp4cr) read: pen4 lowsp4 rst4 resum4 susp4 0d4+d4? write: reset:000000xx $0056 usb sie timing interrupt register (sietir) read: soff eof2f eopf tranf sofie eof2ie eopie tranie write: reset:00000000 $0057 usb sie timing status register (sietsr) read: rstf 0 lockf 00000 write: rstfr lockfr soffr eof2fr eopfr tranfr reset:0*0000000 x = indeterminate = unimplemented figure 14-1. usb i/ o register summary universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 192 universal serial bus module (usb) freescale semiconductor 14.5 overview this usb module is des igned to serve as a compound device. an embedded full-speed devi ce function is combined with a hub in a single usb module. for the hub sub-module, five basic properties can be supported by the hardware or the software: connecti vity behavior, power management, device connect/disconnec t detection, bus fault de tection and recovery, and full/low-speed device traffic control. endpoi nt 0 of the hub sub- module functions as a receive/transmit contro l endpoint. endpoint 1 of the hub sub-module functions as interrupt transfer to report the device change state. $0058 usb hub address register (haddr) read: usben add6 add5 add4 add3 add2 add1 add0 write: reset:0*0000000 * rstf and usben are reset by a power-on reset (por) only. $0059 usb hub interrupt register 0 (hir0) read: txdf rxdf 0 0 txdie rxdie 00 write: txdfr rxdfr reset:00000000 $005b usb hub control register 0 (hcr0) read: tseq stall0 txe rxe tpsiz3 tpsiz2 tpsiz1 tpsiz0 write: reset:00000000 $005c usb hub endpoint 1 control and data register (hcdr) read: stall1 pnew pchg5 pchg4 pchg3 pchg2 pchg1 pchg0 write: reset:00000000 $005d usb hub status register (hsr) read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: tx1str reset:xxx0xxxx $005e usb hub root port control register (hrpcr) read: 0 0 0 resum0 suspnd 0d0+d0? write: reset:000000xx x = indeterminate = unimplemented figure 14-1. usb i/ o register summary universal serial bus module (usb) overview mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 193 for the embedded device sub-module, three types of u sb data transfers are supported: control, interrupt, and bulk (trans mit only). endpoint 0 of the embedded device sub- module functions as a receive/transmit control endpoint. endpoints 1 and 2 of the embedded device sub-module can function as interrup t or bulk, but only in the transmit direction. the block diagram of th e usb module is shown figure 14-2 . the usb module manages communications be tween the host and the usb function. the module is par titioned into eight func tional blocks. these blocks consist of a dual function tran sceiver, the hub rep eater function, the serial interface engi ne (sie), the fram e counter logic, the hub control logic, the embedded device control l ogic, and the endpo int registers. figure 14-2. usb m odule block diagram transceiver hub repeater serial interface engine frame counter registers transceiver d1+ d1? d2+ d2? d3+ d3? d4+ d4? d0+ d0? 12mhz 48mhz cpu bus endpoint 0 8-byte transmit buffer 8-byte receive buffer endpoint 1 8-byte transmit buffer (control endpoint) (interrupt endpoint) hub control logic endpoint 0 8-byte transmit buffer 8-byte receive buffer endpoint 1/2 8-byte transmit buffer (control endpoint) (interrupt/bulk endpoint) embedded device control logic root port downstream ports oscout from osc clock doubler oscxclk from osc 24mhz universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 194 universal serial bus module (usb) freescale semiconductor 14.6 hub function i/o registers the usb hub function prov ides a set of contro l/status registers and sixteen data registers that provide storage for t he buffering of data between the usb hub f unction and the cpu. 14.6.1 usb hub r oot port control register (hrpcr) resum0 ? force resume to the root port this read/write bit forces a resume signal (k state) onto the usb root port data lines to initiate a remote wakeup. software should control the timing of the fo rced resume to be bet ween 10ms and 15ms. reset clears this bit. 1 = force root port da ta lines to k state 0 = default suspnd ? usb sus pend control bit to save power, this read/write bit should be set by the software if a constant idle state for more t han 3ms is detected on the usb bus. setting this bit puts the transceiv er into a power savings mode. this bit also determines the latch sc heme for the data li nes of the root port and the downstream port. when this bit is 1, the current state shown on the data lines wi ll be reflected to the data register (d+/d?) directly. when the bit is 0, the data register s are the latched state sampled at the last eof2 sample point. the hub repeat er?s function is affected by this bit too. the upstream and downstream traffic will be blocked if this bit is set to 1. when the gl obal resume or the downstream remote wakeup signal is found by the suspended hub, address: $005e bit 7654321bit 0 read: 0 0 0 resum0 suspnd 0d0+d0? write: reset:000000xx x = indeterminate = unimplemented figure 14-3. usb hub root po rt control register (hrpcr) universal serial bus module (usb) hub function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 195 software is responsible to propagat e the traffic between the root port and the enabled downstream port by setting the resumx control bit. reset clears this bit. eof2 is generated by the mcu every millisec ond, if sof is not detected when three or more eof2 ha ve occurred, so ftware can set the suspnd bit and put the mcu into suspend mode. d0+, d0? ? root port differential data these read-only bits are the differ ential data shown on the hub root ports. when the suspnd bit is 0, the data is the latched state at the last eof2 sample point. when the suspnd bit is 1, the data reflects the current state on the data line while accessing this register. 14.6.2 usb hub downstream port control registers (hdp1cr?hdp4cr) penx ? downstream po rt enable control bit this read/write bit determines whet her the enabled or disabled state should be assigned to t he downstream port. se tting this bit to 1 enables the port; clearing this bit to 0 disables the port. in the enabled state a full-speed port propagates all downstream signaling; address: $0051?$0054 hrp1cr?hrp4cr bit 7654321bit 0 read: pen1 lowsp1 rst1 resum1 susp1 0d1+d1? write: read: pen2 lowsp2 rst2 resum2 susp2 0d2+d2? write: read: pen3 lowsp3 rst3 resum3 susp3 0d3+d3? write: read: pen4 lowsp4 rst4 resum4 susp4 0d4+d4? write: reset:000000xx x = indeterminate = unimplemented figure 14-4. usb hub downstream port control registers (hdp1cr?hdp4cr) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 196 universal serial bus module (usb) freescale semiconductor a low-speed port propagates downstr eam low-speed packet traffic when preceded by the preamble pid. an enabled por t propagates all upstream signaling incl uding full-speed and low-speed packets. this bit can be set to 1 by the host reques t only. it can be cleared either by hardware when a fault condition was detected or by software through the host request. re set clears this bit. 1 = downstream port is enabled 0 = downstream po rt is disabled lowspx ? full-speed / low -speed port control bit this read/write bit spec ifies the attached devic e in the downstream port is low-speed device or full-speed device. software is responsible to detect the device at tachment and whether a device is full or low-speed. reset clears this bit. 1 = downstream po rt is low-speed 0 = downstream po rt is full-speed note: after a port is enabled, the hub will automatic ally generate a low-speed keep awake signal to t he port every millisecond. rstx ? force reset to the downstream port this read/write bit forces a reset signal ( se0 state) onto the usb downstream port data lines . this bit can be se t by the host request setportfeature (port_reset) only. software should control the timing of the forced reset signali ng downstream for at least 10ms. reset clears this bit. 1 = force downstream port data lines to se0 state 0 = default resumx ? force resume to the downstream port this read/write bit forces a resume signal (k state) onto the usb downstream port data lines. this bit is set to reflect the resume signal when the software detects the remo te resume signal on the data lines of the selective suspend downstream port. downstream selective resume sequence to a port may also be initiated via the host request clearportfeature (port_suspend). software should control the timing of the forced re sume signaling downstream for at least 20ms. universal serial bus module (usb) hub function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 197 to indicate the end of the resume, a low-speed eop signal will be followed when this control bit changes from 1 to 0. reset clears this bit. 1 = force downstream port data lines to k state 0 = default suspx ? downstream port selective suspend bit this read/write bit forces the downstream port entering the selective suspend mode. this bit can be set by the host request setportfeature (port_suspend) only. when this bit is se t, the hub prevents propagating any bus activity (except the port reset or port resume request or the global reset signal) downstream , and the port can only reflect upstream bus state changes via the endpoint 1 of the hub. the blocking occurs at the next eof2 poi nt when this bit is set. reset clears this bit. 1 = force downstream port ent ers the selective suspend mode 0 = default dx+, dx? ? downstream port differential data these read-only bits are the di fferential data shown on the hub downstream ports. when the suspnd bi t is 0 in the hrpcr register, the data is the latched state at th e last eof2 sample point. when the suspnd bit is 1, the data reflects the current state on the data line while accessing this register. universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 198 universal serial bus module (usb) freescale semiconductor 14.6.3 usb sie ti ming interrupt register (sietir) soff ? start of frame detect flag this read-only bit is set when a va lid sof pid is detected on the d0+ and d0? lines at the root port. software must clear this flag by writing a logic 1 to soffr bit in the sietsr register . reset clears this bit. writing to soff has no effect. 1 = start of frame pid has been detected 0 = start of frame pi d has not been detected eof2f ? second end of frame point flag this read-only bit is set when the inte rnal frame timer counts to the bit time that the hub mu st see upstream traffi c terminated near the end of frame. this bit time is defined as 10 bit times from the next start of frame pid. software mu st clear this flag by writing a logic 1 to eof2fr bit in the sietsr register. reset clears this bit. writing to eof2f has no effect. 1 = frame timer counts to the eof2 point 0 = frame timer does not count to the eof2 point eopf ? end of packet detect flag this read-only bit is set when a va lid end of packet sequence is detected on the d0 + and d0? lines. software must clear this flag by writing a logic 1 to the eopfr bit in the sietsr regist er. reset clears this bit. writing to eopf has no effect. 1 = end-of-packet seque nce has been detected 0 = end-of-packet seque nce has not been detected address: $0056 bit 7654321bit 0 read: soff eof2f eopf tranf sofie eof2ie eopie tranie write: reset:00000000 = unimplemented figure 14-5. usb sie timing in terrupt register (sietir) universal serial bus module (usb) hub function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 199 tranf ? bus signal tr ansition detect flag this read-only bit is set if there is any bus acti vity on the upstream or the downstream data lines. generally, this bit is used to wake up the suspended hub when there is any bus activity occurred. software must clear this flag by writing a logic 1 to the tranfr bit in the sietsr register. reset clears this bit. writing to tranf has no effect. 1 = signal transition has been detected 0 = signal transition has not been detected sofie ? start of fr ame interrupt enable this read/write bit enabl es the start of fr ame to generate a usb interrupt when the soff bit becomes set. re set clears this bit. 1 = usb interrupt enabled for start of frame 0 = usb interrupt disabl ed for start of frame eof2ie ? the second end of fr ame point interrupt enable this read/write bi t enables the second end of frame to generate a usb interrupt when the eof2f bit becom es set. reset clears this bit. 1 = usb interrupt en abled for the second end of frame point 0 = usb interrupt disabled for the second end of frame point eopie ? end of packet de tect interrupt enable this read/write bit enabl es the end of fram e to gener ate a usb interrupt when the eopf bit becom es set. reset clears the bit. 1 = usb interrupt enabl ed for end-of-packe t sequence detection 0 = usb interrupt disabled for end-of-packet sequence detection tranie ? bus signal transitio n detect interrupt enable this read/write bit enables the bus signal transition to generate a usb interrupt when the tran f bit becomes set. re set clears this bit. 1 = usb interrupt enabled for bus signal transition 0 = usb interrupt disabled for bus signal transition universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 200 universal serial bus module (usb) freescale semiconductor 14.6.4 usb sie timing st atus register (sietsr) rstf ? usb reset flag this read-only bit is set when a va lid usb reset si gnal state is detected on the d0+ an d d0? lines. this bit is cleared by writing a logic 1 to the rstfr bit or by a mcu power-on reset. 1 = usb reset signal det ected on d0+ and d0? 0 = no usb reset detected rstfr ? clear reset flag bit writing a logic 1 to this write-only bit will clear t he rstf bit if it is set. reset clears this bit. 1 = write 1 to clear the rstf bit 0 = no effect lockf ? usb fram e timer locked this read-only bit is set w hen the internal frame ti mer is locked to the host timer. this bit is cl eared by writing a logic 1 to the lockfr bit. reset clears this bit. 1 = internal frame timer is locked to the host timer 0 = internal frame timer is not locked to the host timer lockfr ? clear frame timer locked flag writing a logic 1 to this write-only bit will clear the lockf bit if it is set. reset clears this bit. 1 = write 1 to clear the lockf bit 0 = no effect address: $0057 bit 7654321bit 0 read: rstf 0 lockf 00000 write: rstfr lockfr soffr eof2fr eopfr tranfr reset:0*0000000 = unimplemented * rstf is reset by a power-on reset (por) only. figure 14-6. usb sie timi ng status register (sietsr) universal serial bus module (usb) hub function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 201 soffr ? start of frame flag reset writing a logic 1 to this write-only bit will clear the soff bit if it is set. reset clears this bit. 1 = write 1 to clear the soff bit 0 = no effect eof2fr ? the second end of frame point flag reset writing a logic 1 to this wr ite-only bit will clear the eof2f bit if it is set. reset clears this bit. 1 = write 1 to clear the eof2f bit 0 = no effect eopfr ? end of pa cket flag reset writing a logic 1 to this write-only bit w ill clear the eopf bit if it is set. reset clears this bit. 1 = write 1 to clear the eopf bit 0 = no effect tranfr ? bus signal tr ansition flag reset writing a logic 1 to this write-only bit will clear the tranf bi t if it is set. reset clears this bit. 1 = write 1 to clear tranf bit 0 = no effect universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 202 universal serial bus module (usb) freescale semiconductor 14.6.5 usb hub addr ess register (haddr) usben ? usb module enable this read/write bit enabl es and disables t he usb module. when usben is cleared, t he usb module will not respond to any tokens. power-on reset clears this bit. 1 = usb module enabled 0 = usb module disabled; usb transce iver is also disabled to save power. add[6:0] ? usb h ub function address these bits specify the address of t he hub function. reset clears these bits. address: $0058 bit 7654321bit 0 read: usben add6 add5 add4 add3 add2 add1 add0 write: reset:0*0000000 * usben is reset by a power-on reset (por) only. figure 14-7. usb hub ad dress register (haddr) universal serial bus module (usb) hub function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 203 14.6.6 usb hub interr upt register 0 (hir0) txdf ? hub endpoint 0 data transmit flag this read-only bit is set after t he data stored in hub endpoint 0 transmit buffers have been sent and an ack handshake packet received from the host. once the next set of data is ready in the transmit buffers, software must clear th is flag by writing a logic 1 to the txdfr bit. to enable the next data packet transmission, txe must also be set. if txdf bit is not cleared, a nak hands hake will be returned in the next in transact ion. txdf generat es an interrupt request to cpu if the tx die bit is also set. writing to txdf has no effect. reset cl ears this bit. 1 = transmit on hub endpoi nt 0 has occurred 0 = transmit on hub endpoint 0 has not occurred rxdf ? hub endpoint 0 data receive flag this read-only bit is set after t he usb hub function has received a data packet and responded with an ack handshake packet. software must clear this flag by writing a logic 1 to th e rxdfr bit after all data received have been read. to enable the next data packet reception, rxe must also be set. if rxdf bi t is not cleared, a nak handshake will be returned in the next out transaction. rxdf generates an interrupt request to cpu if the rxdie bit is also set. writing to rxdf has no effect. reset clears this bit. 1 = receive on hub endpoint 0 has occurred 0 = receive on hub endpoi nt 0 has not occurred address: $0059 bit 7654321bit 0 read: txdf rxdf 0 0 txdie rxdie 00 write: txdfr rxdfr reset:00000000 = unimplemented figure 14-8. usb hub inte rrupt register 0 (hir0) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 204 universal serial bus module (usb) freescale semiconductor txdie ? hub endpoint 0 transmit interrupt enable this read/write bi t enables the txdf bit to generate cpu interrupt request when set. reset clears the txdie bit. 1 = txdf cpu interr upt requests enabled 0 = txdf cpu interrup t requests disabled rxdie ? hub endpoint 0 receive interrupt enable this read/write bi t enables the rxdf bit to generate cpu interrupt request when set. reset clears the rxdie bit. 1 = rxdf cpu interr upt requests enabled 0 = rxdf cpu interr upt requests disabled txdfr ? hub endpoint 0 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txdf bit if it is set. reset clears this bit. 1 = write 1 to clear the txdf bit 0 = no effect rxdfr ? hub endpoint 0 receive flag reset writing a logic 1 to this write-only bit wi ll clear the rxdf bit if it is set. reset clears this bit. 1 = write 1 to clear the rxdf bit 0 = no effect universal serial bus module (usb) hub function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 205 14.6.7 usb hub contro l register 0 (hcr0) tseq ? hub endpoint 0 transmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next hub endpoint 0 transmit 0 = data0 token active for next hub endpoint 0 transmit stall0 ? hub endpoint 0 force stall bit this read/write bit causes hub endpoint 0 to re turn a stall handshake when polled by either an in or out token by the host. the usb hardware clears this bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default txe ? hub endpoint 0 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to the hub endpoint 0. software should set this bit when data is ready to be transmitted. it must be cleared by software when no more hub endpoint 0 data packets needs to be transmitted. if this bit is 0 or the tx df is set, the usb will respond with a nak handshake to any hub endpoint 0 in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready; respond with nak address: $005b bit 7654321bit 0 read: tseq stall0 txe rxe tpsiz3 tpsiz2 tpsiz1 tpsiz0 write: reset:00000000 figure 14-9. usb hub c ontrol register 0 (hcr0) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 206 universal serial bus module (usb) freescale semiconductor rxe ? hub endpoint 0 receive enable this read/write bit enabl es a receive to occur when the usb host controller sends an out token to the hub endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bi t is 0 or the rxdf is set, the usb will respond with a nak handshake to any hub endpoint 0 out tokens. reset clears this bit. 1 = data is ready to be received 0 = not ready for data; respond with nak tpsiz[3:0] ? hub endpoint 0 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for hub endpoint 0. these bits are cleared by reset. 14.6.8 usb hub endpoi nt 1 control and data register (hcdr) stall1 ? hub endpoint 1 force stall bit this read/write bit causes hub endpoint 1 to re turn a stall handshake when polled by the hos t. reset clears this bit. 1 = send stall handshake 0 = default pnew ? port new status change this read/write bi t enables a transmit to occur when the usb host controller sends an in token to hub endpoint 1. so ftware should set this bit when there is a status change on any of the downstream ports, embedded device or hub. it must be cleared by software when there address: $005c bit 7654321bit 0 read: stall1 pnew pchg5 pchg4 pchg3 pchg2 pchg1 pchg0 write: reset:00000000 figure 14-10. usb hub endpoint 1 control and data register (hcdr) universal serial bus module (usb) hub function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 207 is no status change to be reported to the host through endpoint 1. if this bit is 0, a nak handshake will be returned for next in token for hub endpoint 1. reset clears this bit. 1 = port status change bitm ap is ready to be sent 0 = port status does not change; respond with nak pchg5?pchg0 ? hub and port status change bitmap these read/write bits report the status change for the hub, embedded device and the four downstream por ts. the status change bitmap is returned to the host th rough the hub endpoint 1 if the pnew bit is 1. these bits are cleared by reset. bit name function value description pchg0 hub status change 0 no status change in hub 1 hub status change detected pchg1 port 1 status change 0 no status change in port 1 1 port 1 status change detected pchg2 port 2 status change 0 no status change in port 2 1 port 2 status change detected pchg3 port 3 status change 0 no status change in port 3 1 port 3 status change detected pchg4 port 4 status change 0 no status change in port 4 1 port 4 status change detected pchg5 embedded device status change 0 no status change in embedded device 1 embedded device status change detected universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 208 universal serial bus module (usb) freescale semiconductor 14.6.9 usb hub stat us register (hsr) rseq ? hub endpoint 0 receive sequence bit this read-only bit indica tes the type of data packet last received for hub endpoint 0 (data0 or data1). 1 = data1 token received in last hub endpoint 0 receive 0 = data0 token received in last hub endpoint 0 receive setup ? hub setup token detect bit this read-only bit indi cates that a valid setup token has been received. 1 = last token rece ived for hub endpoint 0 was a setup token 0 = last token received for hub endpoi nt 0 was not a setup token tx1st ? hub transmit first flag this read-only bit is se t if the hub endpoint 0 data transmit flag (txdf) is set when the usb control logi c is setting the hub endpoint 0 data receive flag (rxdf). that is, txdf is still set at the end of an endpoint 0 reception. this bit allows the software to know that the endpoint 0 transmission happened before the endpo int 0 reception. reset clears this bit. 1 = in transaction occu rred before setup/out 0 = in transaction occu rred after setup/out tx1str ? clear hub transmit first flag writing a logic 1 to this write-only bit will cl ear the tx1st bit if it is set. reset clears this bit. 1 = write 1 to clear the tx1st bit 0 = no effect address: $005d bit 7654321bit 0 read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: tx1str reset:xxx0xxxx x = indeterminate = unimplemented figure 14-11. usb hub st atus register (hsr) universal serial bus module (usb) embedded device function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 209 rpsiz[3:0] ? hub endpoint 0 receive data packet size these read-only bits store the number of data bytes received for the last out or setup transaction fo r hub endpoint 0. these bits are not affected by reset. 14.6.10 usb hub e ndpoint 0 data regist ers (he0d0?he0d7) he0rx[7:0] ? hub endpoint 0 receive data buffer these read-only bits are serially loaded with out token or setup token data directed at hub endpoint 0. the data is received by the d0+ and d0? pins. he0tx[7:0] ? hub endpoint 0 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in to ken directed at hub endpoint 0. 14.7 embedded device function i/o registers the usb embedded device func tion provides a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the usb embedded device function and the cpu. address: $0030?$0037 he0d0?he0d7 bit 7654321bit 0 read: he0rx7 he0rx6 he0rx5 he0r x4 he0rx3 he0rx2 he0rx1 he0rx0 write: he0tx7 he0tx6 he0tx5 he0t x4 he0tx3 he0tx2 he0tx1 he0tx0 reset: indeterminate after reset figure 14-12. usb hub endpoint 0 data registers (he0d0?he0d7) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 210 universal serial bus module (usb) freescale semiconductor 14.7.1 usb embedded device address register (daddr) deven ? enable u sb embedded device these bit enable or disable the embed ded device function. it is used together with pen1?p en4 to control the enumeration sequence. reset clears these bits. 1 = usb embedded device enabled 0 = usb embedded de vice disabled dadd[6:0] ? usb embedded de vice function address these bits specify the address of the embedded device function. reset clears these bits. 14.7.2 usb embedded device in terrupt register 0 (dir0) txd0f ? embedded device endpo int 0 data transmit flag this read-only bit is set after t he data stored in embedded device endpoint 0 transmit buffers have been sent and an ack handshake packet received from th e host. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd0fr bit. to enable the next data packet transmission, address: $0048 bit 7654321bit 0 read: deven dadd6 dadd5 dadd4 dadd3 dadd2 dadd1 dadd0 write: reset:00000000 figure 14-13. usb em bedded device address register (daddr) address: $0049 bit 7654321bit 0 read: txd0f rxd0f 0 0 txd0ie rxd0ie 00 write: txd0fr rxd0fr reset:00000000 = unimplemented figure 14-14. usb embedded device interrupt register 0 (dir0) universal serial bus module (usb) embedded device function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 211 tx0e must also be set. if txd0f bit is not cleared, a nak handshake will be returned in the next in transacti on. txd0f generates an interrupt request to the cpu if the txd0ie bit is also set. writing to txd0f has no effect. re set clears this bit. 1 = transmit on embedded devic e endpoint 0 has occurred 0 = transmit on embedded device endpoint 0 has not occurred rxd0f ? embedded device end point 0 data receive flag this read-only bit is set after the usb embedded dev ice module has received a data packet and re sponded with an ack handshake packet. software must clear this fl ag by writing a logic 1 to the rxd0fr bit after all data receiv ed have been r ead. to enable the next data packet reception, rx0e must also be set. if rxd0f bit is not cleared, a nak handshake will be returned in the next out transaction. rxd0f generates an inte rrupt request to cpu if the rxd0ie bit is also se t. writing to rxd0f has no effect. reset clears this bit. 1 = receive on embedded devi ce endpoint 0 has occurred 0 = receive on embedded device endpoint 0 has not occurred txd0ie ? embedded device endpoint 0 transmit interrupt enable this read/write bi t enables the txd0f bit to generate cpu interrupt request when set. reset cl ears the txd0ie bit. 1 = txd0f cpu interr upt requests enabled 0 = txd0f cpu interr upt requests disabled rxd0ie ? embedded device endpoin t 0 receive interrupt enable this read/write bi t enables the rxd0f bit to generate cpu interrupt request when set. reset cl ears the rxd0ie bit. 1 = rxd0f cpu interr upt requests enabled 0 = rxd0f cpu interr upt requests disabled txd0fr ? embedded device en dpoint 0 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd0f bit if it is set. reset clears this bit. 1 = write 1 to clear txd0f bit 0 = no effect universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 212 universal serial bus module (usb) freescale semiconductor rxd0fr ? embedded device e ndpoint 0 receive flag reset writing a logic 1 to this write-only bit will clear the rxd0f bit if it is set. reset clears this bit. 1 = write 1 to clear rxd0f bit 0 = no effect 14.7.3 usb embedded device in terrupt register 1 (dir1) txd1f ? embedded device endpo int 1/2 data transmit flag this read-only bit is shared by endpoint 1 and endpo int 2 of the embedded device. it is set after the data stored in the shared endpoint 1/2 transmit buffer of t he embedded device have been sent and an ack handshake packe t received from the hos t. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd1fr bit. to enable th e next data packet transmission, tx1e must al so be set. if txd1f bit is not cleared, a nak handshake will be retur ned in the next in transaction. txd1f generates an interrupt request to the cpu if the txd1ie bit is also set. writing to txd1f has no effect. reset clears this bit. 1 = transmit on endpoint 1 or endpoint 2 of the embedded device has occurred 0 = transmit on endpoint 1 or endpoint 2 of the embedded device has not occurred txd1ie ? embedded device endpoint 1/2 transmi t interrupt enable this read/write bi t enables the txd1f bit to generate cpu interrupt request when set. reset cl ears the txd1ie bit. 1 = txd1f cpu interr upt requests enabled 0 = txd1f cpu interr upt requests disabled address: $004a bit 7654321bit 0 read: txd1f 0 0 0 txd1ie 000 write: txd1fr reset:00000000 = unimplemented figure 14-15. usb embedded device interrupt register 1 (dir1) universal serial bus module (usb) embedded device function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 213 txd1fr ? embedded device endpoi nt 1/2 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd1f bit if it is set. reset clears this bit. 1 = write 1 to clear txd1f 0 = no effect 14.7.4 usb embedded device c ontrol register 0 (dcr0) t0seq ? embedded device endpoi nt 0 transmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next embedded device endpoint 0 transmit 0 = data0 token active for next embedded device endpoint 0 transmit dstall0 ? embedded de vice endpoint 0 force stall bit this read/write bit caus es embedded device endpoi nt 0 to return a stall handshake when polle d by either an in or out token by the host. the usb hardware clears th is bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default address: $004b bit 7654321bit 0 read: t0seq dstall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 figure 14-16. usb embedded device control register 0 (dcr0) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 214 universal serial bus module (usb) freescale semiconductor tx0e ? embedded device e ndpoint 0 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to the embedded device endpoint 0. software should set this bit when dat a is ready to be transmitted. it must be cleared by software when no more embedded device endpoint 0 data needs to be transmitted. if this bit is 0 or the txd0f is set, the usb will respond with a nak handshake to any embedded device endpoint 0 in tokens . reset clears this bit. 1 = data is ready to be sent 0 = data is not ready; respond with nak rx0e ? embedded device e ndpoint 0 re ceive enable this read/write bit enabl es a receive to occur when the usb host controller sends an out token to the embedded device endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software w hen data cannot be receiv ed. if this bit is 0 or the rxd0f is set, the usb will respond wi th a nak handshake to any embedded device endpoint 0 out tokens. reset clears this bit. 1 = data is ready to be received 0 = not ready for data; respond with nak tp0siz[3:0] ? embedded device endpoi nt 0 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for embedded devi ce endpoint 0. these bits are cleared by reset. universal serial bus module (usb) embedded device function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 215 14.7.5 usb embedded device c ontrol register 1 (dcr1) t1seq ? embedded device endpoi nt 1/2 transmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed to embedded device endpoint 1 or 2. toggl ing of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next embedded devi ce endpoint 1/2 transmit 0 = data0 token active for next embedded devi ce endpoint 1/2 transmit endadd ? endpoint address select this read/write bit s pecifies whether the data inside the de1d0?de1d7 register s are used for embedd ed device endpoint 1 or 2. if all the conditions for a successful endpoint 2 usb response to a host?s in token are satisfied (txd1f=0, tx1e=1, dstall2=0, and enable2=1) except that the endadd bit is configured for endpoint 1, the usb responds with a nak handshake packet. reset clears this bit. 1 = the data buffers are used for embedded device endpoint 2 0 = the data buffers are used for embedded device endpoint 1 tx1e ? embedded device endpo int 1/2 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to endpoint 1 or endpoint 2 of the embedded device. the appropria te endpoint enable bit, enable1 or enable2 bit in the dcr 2 register, should al so be set. software should set the tx1e bit when dat a is ready to be transmitted. address: $004c bit 7654321bit 0 read: t1seq endadd tx1e 0 tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 = unimplemented figure 14-17. usb embedded device control register 1 (dcr1) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 216 universal serial bus module (usb) freescale semiconductor it must be cleared by software when no more data needs to be transmitted. if this bit is 0 or the txd1f is se t, the usb w ill respond with a nak handshake to any endpoint 1 or end point 2 directed in tokens. reset clears this bit. 1 = data is ready to be sent. 0 = data is not ready; respond with nak. tp1siz[3:0] ? embedded device endpoint 1/2 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for embedded device endpoint 1 or endpoint 2. these bits are cleared by reset. 14.7.6 usb embedded device c ontrol register 2 (dcr2) enable2 ? embedded devi ce endpoint 2 enable this read/write bit enables embedded device endpoint 2 and allows the usb to respond to in packets addressed to this endpoint. reset clears this bit. 1 = embedded device endpoint 2 is enabled and can respond to an in token 0 = embedded device endpoi nt 2 is disabled enable1 ? embedded devi ce endpoint 1 enable this read/write bit enables embedded device endpoint 1 and allows the usb to respond to in packets addressed to this endpoint. reset clears this bit. 1 = embedded device endpoint 1 is enabled and can respond to an in token 0 = embedded device endpoi nt 1 is disabled address: $0047 bit 7654321bit 0 read: 0000 enable2 enable1 dstall2 dstall1 write: reset:00000000 = unimplemented figure 14-18. usb embedded device control register 2 (dcr2) universal serial bus module (usb) embedded device function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 217 dstall2 ? embedded de vice endpoint 2 force stall bit this read/write bit caus es embedded device endpoi nt 2 to return a stall handshake when polle d by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default dstall1 ? embedded de vice endpoint 1 force stall bit this read/write bit caus es embedded device endpoi nt 1 to return a stall handshake when polle d by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default 14.7.7 usb embedded device status register (dsr) drseq ? embedded devi ce endpoint 0 receive sequence bit this read-only bit indica tes the type of data packet last received for embedded device endpoint 0 (data0 or data1). 1 = data1 token received in last embedded device endpoint 0 receive 0 = data0 token received in last embedded device endpoint 0 receive dsetup ? embedded device se tup token detect bit this read-only bit indi cates that a valid setup token has been received. 1 = last token rece ived for endpoint 0 was a setup token 0 = last token receiv ed for endpoint 0 was not a setup token address: $004d bit 7654321bit 0 read: drseq dsetup dtx1st 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: dtx1str reset:00000000 = unimplemented figure 14-19. usb embedded device status register (dsr) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 218 universal serial bus module (usb) freescale semiconductor dtx1st ? embedded device transmit first flag this read-only bit is set if t he embedded device endpoint 0 data transmit flag (txd0f) is set when the usb control logic is setting the embedded device endpoint 0 data re ceive flag (rxd0f). that is, txd0f is still set at the end of an endpoint 0 recept ion. this bit allows the software to know that th e endpoint 0 transmission happened before the endpoint 0 recepti on. reset clears this bit. 1 = in transaction occu rred before setup/out 0 = in transaction occu rred after setup/out dtx1str ? clear transmit first flag writing a logic 1 to this write-only bit will clear t he dtx1st bit if it is set. reset clears this bit. 1 = write 1 to clear dtx1st bit 0 = no effect rp0siz[3:0] ? embedded device endpoi nt 0 receive data packet size these read-only bits store the number of data bytes received for the last out or setup transacti on for embedded device endpoint 0. these bits are not affected by reset. universal serial bus module (usb) embedded device function i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor univers al serial bus module (usb) 219 14.7.8 usb embedded devi ce endpoint 0 data regi sters (de0d0?de0d7) de0rx[7:0] ? embedded device e ndpoint 0 receive data buffer these read-only bits are serially loaded with out token or setup token data directed at embedded device endpoint 0. the data is received by the d0+ and d0? pins. de0tx[7:0] ? embedded device e ndpoint 0 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in to ken directed at embedded device endpoint 0. 14.7.9 usb embedded devi ce endpoint 1/2 data r egisters (de1d0?de1d7) de1tx[7:0] ? embedded device endpoint 1/ endpoint 2 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in to ken directed at endpoint 1 or endpoint 2 of the embe dded device. these buffers are shared by embedded device endpoints 1 an d 2 and depend on proper configuration of the endadd bit. address: $0020?$0027 de0d0?de0d7 bit 7654321bit 0 read: de0rx7 de0rx6 de0rx5 de0r x4 de0rx3 de0rx2 de0rx1 de0rx0 write: de0tx7 de0tx6 de0tx5 de0t x4 de0tx3 de0tx2 de0tx1 de0tx0 reset: indeterminate after reset figure 14-20. usb embedded device endpoint 0 data registers (de0d0?de0d7) address: $0028?$002f de1d0?de1d7 bit 7654321bit 0 read: write: de1tx7 de1tx6 de1tx5 de1t x4 de1tx3 de1tx2 de1tx1 de1tx0 reset: indeterminate after reset figure 14-21. usb em bedded device endpoint 1/ 2 data registers (de1d0?de1d7) universal serial bus module (usb) data sheet mc68hc908ld64 ? rev. 3.0 220 universal serial bus module (usb) freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 221 data sheet ? mc68hc908ld64 section 15. multi-master iic interface (mmiic) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.5 multi-master iic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.5.1 multi-master iic address regist er (mmadr) . . . . . . . . . . 224 15.5.2 multi-master iic control register (mmcr) . . . . . . . . . . . . 225 15.5.3 multi-master iic ma ster control register (mimcr) . . . . . . 226 15.5.4 multi-master iic stat us register (mmsr) . . . . . . . . . . . . . 228 15.5.5 multi-master iic data transm it register (mmdtr) . . . . . . 230 15.5.6 multi-master iic data receiv e register (mmdrr ) . . . . . . 231 15.6 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.2 introduction this multi-master iic (mmi ic) interface is designe d for internal serial communication between the mcu and other iic devices. a hardware circuit generates "start" and "stop" signal, while byte by byte data transfer is interrupt driven by the so ftware algorithm. therefore, it can greatly help the software in dealin g with other devices to have higher system efficiency in a typi cal digital monitor system. this module not only can be applied in internal co mmunications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. it also prov ides the flexib ility of hooking additional devices to an existing sys tem for future expansion without adding extra hardware. multi-master iic interface (mmiic) data sheet mc68hc908ld64 ? rev. 3.0 222 multi-master iic interface (mmiic) freescale semiconductor this multi-master iic module uses t he iicscl clock lin e and the iicsda data line to communicate wi th external ddc host or iic interface. these two pins are shared with port pins ptd6 and ptd7 respectively. the outputs of iicsda and ii cscl pins are open-dr ain type ? no clamping diode is connected betwe en the pin and internal v dd . the maximum data rate typically is 750k-bps. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pf. 15.3 features compatibility with multi-master iic bus standard software controllable a cknowledge bit generation interrupt driven byte by byte data transfer calling address iden tification interrupt auto detection of r/w bit and switching of transmit or receive mode detection of start, repeat ed start, and stop signals auto generation of start and stop condition in master mode arbitration loss detection and no -ack awareness in master mode 8 selectable baud ra te master clocks automatic recognition of th e received acknowledge bit 15.4 i/o pins the mmiic module uses two i/o pins , shared with standard port i/o pins. the full name of the mmiic i/o pins are listed in table 15-1 . the generic pin name appear in the text that follows. table 15-1. pin name conventions mmiic generic pin names: full mcu pin names: pin selected for iic function by: sda ptd7/iicsda iicdate bit in pdcr ($0069) scl ptd6/iicscl iicscle bit in pdcr ($0069) multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 223 15.5 multi-master iic registers six registers are associ ated with the multi-master iic module, they are outlined in the following sections. addr.register name bit 7654321bit 0 $006a multi-master iic master control register (mimcr) read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: 0 0 reset:00000000 $006b multi-master iic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $006c multi-master iic control register (mmcr) read: mmen mmien 00 mmtxak 000 write: reset:00000000 $006d multi-master iic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 $006e multi-master iic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 $006f multi-master iic data receive register (mmdrr) read: mmrd7 mmrd6 mmrd5 mmrd4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 = unimplemented figure 15-1. mmiic i/ o register summary multi-master iic interface (mmiic) data sheet mc68hc908ld64 ? rev. 3.0 224 multi-master iic interface (mmiic) freescale semiconductor 15.5.1 multi-master iic address register (mmadr) mmad[7:1] ? multi-master address these seven bits can be the mmiic interface? s own specific slave address in slave mode or the call ing address when in master mode. software must update it as the calling address while entering the master mode and restore it s own slave address af ter the master mode is relinquished. reset se ts a default value of $a0. mmextad ? multi-mast er expanded address this bit is set to ex pand the address of the mmiic in slave mode. when set, the mmiic will acknowledge the general call address $00 and the matched 4-bit address, mm ad[7:4]. reset clears this bit. for example, when mm adr is configured as: the mmiic module will res pond to the ca lling address: or the general calling address: where x = don?t care; bit 0 of the ca lling address is t he mmrw bit from the calling master. 1 = mmiic responds to address $00 and $mmad[7:4] 0 = mmiic responds to address $mmad[7:1] address: $006b bit 7654321bit 0 read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 figure 15-2. multi- master iic address register (mmadr) mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad 1 mmextad 1101xxx1 bit 765432bit 1 1101xxx 0000000 multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 225 15.5.2 multi-master iic control register (mmcr) mmen ? multi-master iic enable this bit is set to enable the multi-mast er iic module. when mmen = 0, module is disabled and all flags will restor e to its power- on default states. reset clears this bit. 1 = mmiic module enabled 0 = mmiic module disabled mmien ? multi-master iic interrupt enable when this bit is set, the mmtx if, mmrxif, mmalif, and mmnakif flags are enabled to generate an in terrupt request to the cpu. when mmien is cleared, the these flags are prevented from generating an interrupt request. re set clears this bit. 1 = mmtxif, mmrxif, mmalif, and/or mmnakif bit set will generate interrupt request to cpu 0 = mmtxif, mmrxif, mmalif, a nd/or mmnakif bit set will not generate interrupt request to cpu mmtxak ? transmit acknowledge enable this bit is set to disable the mmiic from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. when mmtxak is cleared, an acknowledge signal wi ll be sent at the 9th clock bit. reset clears this bit. 1 = mmiic does not send ackno wledge signals at 9th clock bit 0 = mmiic sends acknowledge signal at 9th clock bit address: $006c bit 7654321bit 0 read: mmen mmien 00 mmtxak 000 write: reset:00000000 = unimplemented figure 15-3. multi-master iic control register (mmcr) multi-master iic interface (mmiic) data sheet mc68hc908ld64 ? rev. 3.0 226 multi-master iic interface (mmiic) freescale semiconductor 15.5.3 multi-master iic master control regi ster (mimcr) mmalif ? multi-master arbi tration lost interrupt flag this flag is set when software atte mpt to set mmast but the mmbb has been set by detecting the start condition on the lin es or when the mmiic is transmitting a "1" to sd a line but detecte d a "0" from sda line in master mode ? an arbitration loss. this bit generates an interrupt request to the cpu if th e mmien bit in mmcr is also set. this bit is cleared by writi ng "0" to it or by reset. 1 = lost arbitrati on in master mode 0 = no arbitration lost mmnakif ? no acknowledge interrupt flag this flag is only set in master mode (mmast = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. this flag also clear s mmast. mmnakif generates an interrupt request to cpu if the mmie n bit in mmcr is also set. this bit is cleared by writing "0" to it or by reset. 1 = no acknowl edge bit detected 0 = acknowledg e bit detected mmbb ? bus busy flag this flag is set after a start conditi on is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the mmiic is disabled. reset clears this bit. 1 = start condition detected 0 = stop condition detected or mmiic is disabled address: $006a bit 7654321bit 0 read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: 0 0 reset:00000000 figure 15-4. multi-master iic ma ster control register (mimcr) multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 227 mmast ? master control bit this bit is set to initia te a master mode transf er. in master mode, the module generates a star t condition to the sda and scl lines, followed by sending the calli ng address stored in mmadr. when the mmast bit is cleared by mmnakif set (no acknowledge) or by software, the mo dule generates the stop condition to the lines after the current byte is transmitted. if an arbitration loss occurs (mmali f = 1), the module reverts to slave mode by clearing mmast, and releasing sda and scl lines immediately. this bit is cleared by writi ng "0" to it or by reset. 1 = master mode operation 0 = slave mode operation mmrw ? master read/write this bit will be tr ansmitted out as bit 0 of th e calling address when the module sets the mmast bit to ent er master mode. the mmrw bit determines the transfer direction of the data bytes that follows. when it is "1", the module is in master receive mode. when it is "0", the module is in master transmit mode. reset clears this bit. 1 = master mode receive 0 = master mode transmit mmbr2?mmbr0 ? baud rate select these three bits select one of eigh t clock rates as the master clock when the module is in master mode. since this master clock is deri ved the cpu bus cl ock, the user program should not execute the wa it instruction when the mmiic module in master mode. this will cause the sda and scl lines to hang, as the wait instruction places the mcu in wait mode, with cpu clock is halted. these bits are cleared upon reset. (see table 15-2 . baud rate select .) multi-master iic interface (mmiic) data sheet mc68hc908ld64 ? rev. 3.0 228 multi-master iic interface (mmiic) freescale semiconductor 15.5.4 multi-master iic status register (mmsr) mmrxif ? multi-master ii c receive interrupt flag this flag is set after the data receiv e register (mmdrr) is loaded with a new received data. once the mm drr is loaded with received data, no more received data can be loaded to the mmdrr register until the cpu reads the data from the mmdrr to clear mmrxbf flag. mmrxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or by reset; or when the mmen = 0. 1 = new data in data re ceive register (mmdrr) 0 = no data received table 15-2. baud rate select mmbr2 mmbr1 mmbr0 baud rate 000 750k 001 375k 0 1 0 187.5k 011 93.75k 100 46.875k 101 23.437k 110 11.719k 1 1 1 5.859k note: cpu bus clock is external clock 4 = 6mhz address: $006d bit 7654321bit 0 read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 = unimplemented figure 15-5. multi-master ii c status register (mmsr) multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 229 mmtxif ? multi-master transmit interrupt flag this flag is set when data in the data transmit regi ster (mmdtr) is downloaded to the output circuit, and that new data ca n be written to the mmdtr. mmtxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or when the mmen = 0. 1 = data transfer completed 0 = data transfer in progress mmatch ? multi-master address match this flag is set when the received data in the data receive register (mmdrr) is an calling address whic h matches with the address or its extended addresses (mmextad=1) specified in the mmadr register. 1 = received address matches mmadr 0 = received address does not match mmsrw ? multi-master slave read/write this bit indicates the data direction when the module is in slave mode. it is updated after t he calling address is rece ived from a master device. mmsrw = 1 when the calling ma ster is reading data from the module (slave transmit mode). mmsrw = 0 when the master is writing data to the m odule (receive mode). 1 = slave mode transmit 0 = slave mode receive mmrxak ? multi-master receive acknowledge when this bit is clear ed, it indicate s an acknowledge signal has been received after the comp letion of 8 data bits transmission on the bus. when mmrxak is set, it indicates no acknow ledge signal has been detected at the 9th clo ck; the module will releas e the sda line for the master to generate "stop" or "repeated start" condi tion. reset sets this bit. 1 = no acknowledge signal received at 9th clock bit 0 = acknowledge signal re ceived at 9th clock bit multi-master iic interface (mmiic) data sheet mc68hc908ld64 ? rev. 3.0 230 multi-master iic interface (mmiic) freescale semiconductor mmtxbe ? multi-master transmit buffer empty this flag indicates the status of th e data transmit r egister (mmdtr). when the cpu writes the data to the mmdtr, the mmtxbe flag will be cleared. mmtxbe is se t when mmdtr is empt ied by a transfer of its data to the out put circuit. reset sets this bit. 1 = data transmit register empty 0 = data transmit register full mmrxbf ? multi-master receive buffer full this flag indicates the status of th e data receive register (mmdrr). when the cpu reads the data from the mmdrr, the mmrxbf flag will be cleared. mmrx bf is set when mmdrr is full by a transfer of data from the input circ uit to the mmdrr. re set clears this bit. 1 = data receive register full 0 = data receive register empty 15.5.5 multi-master iic data transmit register (mmdtr) when the mmiic module is enabled, mmen = 1, data written into this register depends on whether module is in master or slave mode. in slave mode, the data in mmdtr will be transferr ed to the out put circuit when: the module detects a matched calling addres s (mmatch = 1), with the calling master requesting data (mmsrw = 1); or the previous data in the output circuit has be tr ansmitted and the receiving master returns an a cknowledge bit, indicated by a received acknowl edge bit (mmrxak = 0). address: $006e bit 7654321bit 0 read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 figure 15-6. multi-master iic da ta transmit register (mmdtr) multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 231 if the calling master does not re turn an acknowledge bit (mmrxak = 1), the module will release the sda line for master to generate a "stop" or "repeated start" condition. the data in the mmdtr will not be transferred to the output circuit until the nex t calling from a master. the transmit buffer empty flag remains cleared (mmtxbe = 0). in master mode, the dat a in mmdtr will be tr ansferred to the output circuit when: the module receives an acknow ledge bit (mmr xak = 0), after setting master transmit m ode (mmrw = 0), and the calling address has been transmitted; or the previous data in the output circuit has be tr ansmitted and the receiving slave retu rns an acknowledge bi t, indicated by a received acknowl edge bit (mmrxak = 0). if the slave does not return an acknowledge bit (mmrxak = 1), the master will gener ate a "stop" or "repeated start" condition. th e data in the mmdtr will not be trans ferred to the output circuit. the transmit buffer empty flag remains cleared (mmtxbe = 0). the sequence of events for slave tr ansmit and master transmit are illustrated in figure 15-8 . 15.5.6 multi-master iic da ta receive regi ster (mmdrr) when the mmiic module is enabled, mmen = 1, data in this read-only register depends on whether module is in master or slave mode. address : $006f bit 7654321bit 0 read: mmrd7 mmrd6 mmrd5 mmrd4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 = unimplemente d figure 15-7. multi-master iic data receive r egister (mmdrr) multi-master iic interface (mmiic) data sheet mc68hc908ld64 ? rev. 3.0 232 multi-master iic interface (mmiic) freescale semiconductor in slave mode, t he data in mmdrr is: the calling address from the ma ster when the address match flag is set (mmatch = 1); or the last data received when mmatch = 0. in master mode, the data in the mmdrr is: the last data received. when the mmdrr is read by the cpu, the receive buffer full flag is cleared (mmrxbf = 0), and the next re ceived data is loaded to the mmdrr. each time when new data is loaded to the mmdrr, the mmrxif interrupt flag is set, indicati ng that new data is available in mmdrr. the sequence of events for slave receive and master receive are illustrated in figure 15-8 . 15.6 programmin g considerations when the mmiic module detects an arbi tration loss in ma ster mode, it will release both sda and scl lines im mediately. but if there are no further stop condi tions detected, the module will hang up. therefore, it is recommended to have time-out soft ware to recover from such ill condition. the software can start the ti me-out counter by looking at the mmbb (bus busy) flag in the mimcr and rese t the counter on the completion of one byte tr ansmission. if a time-out occur, software can clear the mmen bit (disable mmiic module) to rele ase the bus, and hence clearing the mm bb flag. this is the onl y way to clear the mmbb flag by software if the module hangs up due to a no stop condition received. the mmiic c an resume operation again by setting the mmen bit. multi-master iic interface (mmiic) programming considerations mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor multi-master iic interface (mmiic) 233 figure 15-8. data transf er sequences for master/sla ve transmit/receive modes start address ack tx data1 mmtxbe=0 mmrw=0 mmast=1 mmtxif=1 mmtxbe=1 mmnakif=1 mmast=0 mmtxbe=1 (a) master transmit mode (b) master receive mode (c) slave transmit mode mmtxif=1 mmtxbe=0 ack tx datan nak stop mmtxif=1 mmtxbe=1 start address ack rx data1 mmrxbf=0 mmast=1 mmtxbe=0 mmrxbf=1 mmrxif=1 mmnakif=1 mmast=0 mmrxif=1 mmrxbf=1 ack rx datan nak stop 1 start address ack tx data1 mmtxbe=1 mmrxbf=0 mmnakif=1 mmtxbe=0 mmtxbe=1 (d) slave receive mode mmtxif=1 ack tx datan nak stop mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=1 mmtxif=1 mmtxbe=1 0 start address ack rx data1 mmrxbf=1 mmrxif=1 mmrxif=1 mmrxbf=1 ack rx datan nak stop mmtxbe=0 mmrxbf=0 mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=0 data1 mmdrr datan mmdrr data1 mmdtr data2 mmdtr datan+2 mmdtr data1 mmdtr data2 mmdtr data3 mmdtr datan+2 mmdtr (dummy data mmdtr) mmrw=1 data1 mmdrr datan mmdrr 0 1 key: shaded data packets indicate a transmit by the mcu?s mmiic module multi-master iic interface (mmiic) data sheet mc68hc908ld64 ? rev. 3.0 234 multi-master iic interface (mmiic) freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 235 data sheet ? mc68hc908ld64 section 16. ddc12ab interface 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16.5 ddc protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.6 ddc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.6.1 ddc address register (ddcadr) . . . . . . . . . . . . . . . . . . 238 16.6.2 ddc2 address register (ddc2adr ) . . . . . . . . . . . . . . . . 239 16.6.3 ddc control register (ddccr) . . . . . . . . . . . . . . . . . . . . 240 16.6.4 ddc master control register (ddcmcr) . . . . . . . . . . . . . 241 16.6.5 ddc status register (ddcsr) . . . . . . . . . . . . . . . . . . . . . 244 16.6.6 ddc data transmit register ( ddcdtr) . . . . . . . . . . . . . . 246 16.6.7 ddc data receive register (d dcdrr) . . . . . . . . . . . . . . 247 16.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.2 introduction this ddc12ab interface module is used by the digital monitor to show its identification informat ion to the video contro ller. it contains ddc1 hardware and a two-wire, bidirectional serial bus which is fully compatible with multi-master ii c bus protocol to support ddc2ab interface. this module not only can be applied in internal co mmunications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. it also prov ides the flexib ility of hooking additional devices to an existing sys tem for future expansion without adding extra hardware. ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 236 ddc12ab interface freescale semiconductor this ddc12ab module uses the ddcscl clock li ne and the ddcsda data line to communicate wi th external ddc host or iic interface. these two pins are shared with port pins ptd4 and ptd5 respectively. the outputs of ddcsda and ddcscl pins are open-drain type ? no clamping diode is connected bet ween the pin and internal v dd . the maximum data rate typically is 100 k-bps. the maximum communication length and the number of devices that can be c onnected are limited by a maximum bus capa citance of 400pf. 16.3 features ddc1 hardware compatibility with multi-master iic bus standard software controllable a cknowledge bit generation interrupt driven byte by byte data transfer calling address iden tification interrupt auto detection of r/w bit and switching of transmit or receive mode detection of start, repeat ed start, and stop signals auto generation of start and stop condition in master mode arbitration loss detection and no -ack awareness in master mode 8 selectable baud ra te master clocks automatic recognition of th e received acknowledge bit 16.4 i/o pins the ddc12ab module uses two i/o pi ns, shared with standard port i/o pins. the full name of the ddc 12ab i/o pins are listed in table 16-1 . the generic pin name appear in the text that follows. table 16-1. pin name conventions ddc12ab generic pin names: full mcu pin names: pin selected for ddc function by: sda ptd5/ddcsda ddcdate bit in pdcr ($0069) scl ptd4/ddcscl ddcscle bit in pdcr ($0069) ddc12ab interface i/o pins mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 237 addr.register name bit 7654321bit 0 $0016 ddc master control register (ddcmcr) read: alif nakif bb mast mrw br2 br1 br0 write: 00 reset:00000000 $0017 ddc address register (ddcadr) read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 $0018 ddc control register (ddccr) read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 $0019 ddc status register (ddcsr) read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 $001a ddc data transmit register (ddcdtr) read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 $001b ddc data receive register (ddcdrr) read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 $001c ddc2 address register (ddc2adr) read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 = unimplemented figure 16-1. ddc i/o register summary ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 238 ddc12ab interface freescale semiconductor 16.5 ddc protocols in ddc1 protocol comm unication, the module is in transmit mode. the data written to the transmi t register is continuou sly clocked out to the sda line by the rising edge of th e vsync input si gnal. during ddc1 communication, a falling transition on the sc l line can be detected to generate an interrupt to t he cpu for mode switching. in ddc2ab protocol co mmunication, the modu le can be either in transmit mode or in rece ive mode, contro lled by the calling master. in ddc2 protocol comm unication, the module wil l act as a standard iic module, able to act as a master or a slave device. 16.6 ddc registers seven registers are associated with the ddc module, t hey are outlined in the following sections. 16.6.1 ddc address register (ddcadr) dad[7:1] ? ddc address these seven bits can be the ddc2 interface?s own specific slave address in slave mode or the call ing address when in master mode. software must update it as the calling address while entering the master mode and restore it s own slave address af ter the master mode is relinquished. reset se ts a default value of $a0. address: $0017 bit 7654321bit 0 read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 figure 16-2. ddc addr ess register (ddcadr) ddc12ab interface ddc registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 239 extad ? ddc expanded address this bit is set to exp and the address of the d dc in slave mode. when set, the ddc will acknowledge th e general call address $00 and the matched 4-bit addres s, dad[7:4]. reset clears this bit. for example, when d dcadr is configured as: the ddc module will respon d to the calling address: or the general calling address: where x = don?t care; bit 0 of the calling address is the mrw bit from the calling master. 1 = ddc responds to addr ess $00 and $dad[7:4] 0 = ddc responds to address $dad[7:1] 16.6.2 ddc2 address r egister (ddc2adr) d2ad[7:1] ? ddc2 address these seven bits represent the sec ond slave address for the ddc2bi protocol. d2ad[7:1] shoul d be set to the same value as dad[7:1] in ddcadr if user applicati on do not use ddc2bi. re set clears all bits this register. dad7 dad6 dad5 dad4 dad3 dad2 dad 1 extad 1101xxx1 bit 765432bit 1 1101xxx 0000000 address: $001c bit 7654321bit 0 read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 figure 16-3. ddc2 addr ess register (ddc2adr) ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 240 ddc12ab interface freescale semiconductor 16.6.3 ddc contro l register (ddccr) den ? ddc enable this bit is set to ena ble the ddc module. w hen den = 0, module is disabled and all flags will restore to its power-o n default states. reset clears this bit. 1 = ddc module enabled 0 = ddc module disabled dien ? ddc interrupt enable when this bit is set, the txif, rxif, alif, and nakif flags are enabled to generate an inte rrupt request to the cpu. when dien is cleared, the these flag s are prevented from generating an interrupt request. reset clears this bit. 1 = txif, rxif, alif, and/or naki f bit set will generate interrupt request to cpu 0 = txif, rxif, alif, and/or n akif bit set will not generate interrupt request to cpu txak ? transmit a cknowledge enable this bit is set to dis able the ddc from sendi ng out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. when txak is cleared, an acknowledge si gnal will be sent at the 9th clock bit. reset clears this bit. 1 = ddc does not send acknowl edge signals at 9th clock bit 0 = ddc sends ac knowledge signal at 9th clock bit address: $0018 bit 7654321bit 0 read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 = unimplemented figure 16-4. ddc cont rol register (ddccr) ddc12ab interface ddc registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 241 sclien ? scl interrupt enable when this bit is set, the sclif flag is enabled to generate an interrupt request to the cpu. when sclien is cleared, sclif is prevented from generating an interrupt request. reset clears this bit. 1 = sclif bit set will genera te interrupt request to cpu 0 = sclif bit set wi ll not generate interr upt request to cpu ddc1en ? ddc1 pr otocol enable this bit is set to ena ble ddc1 protocol. the ddc 1 protocol will use the vsync input (from sync processor) as the master clock input to the ddc module. vsync risi ng-edge will c ontinuously clock out the data to the output circuit. no calli ng address comparison is performed. the srw bit in ddc status register (ddcsr) will always read as "1". reset clears this bit. 1 = ddc1 protocol enabled 0 = ddc1 protocol disabled 16.6.4 ddc master co ntrol register (ddcmcr) alif ? ddc arbitratio n lost interrupt flag this flag is set when software atte mpt to set mast but the bb has been set by detecting the st art condition on the lines or when the ddc is transmitting a "1" to sda line but detected a "0" from sda line in master mode ? an ar bitration loss. this bi t generates an interrupt request to the cpu if the dien bit in ddccr is also se t. this bit is cleared by writing "0" to it or by reset. 1 = lost arbitrati on in master mode 0 = no arbitration lost address: $0016 bit 7654321bit 0 read: alif nakif bb mast mrw br2 br1 br0 write: 00 reset:00000000 figure 16-5. ddc master control regist er (ddcmcr) ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 242 ddc12ab interface freescale semiconductor nakif ? no acknowledge interrupt flag this flag is only set in master mo de (mast = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. this flag also clears mast. nakif generat es an interrupt request to cpu if the dien bit in ddccr is also set. this bit is cleared by writing "0" to it or by reset. 1 = no acknowl edge bit detected 0 = acknowledg e bit detected bb ? bus busy flag this flag is set after a start conditi on is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the ddc is disabled. reset clears this bit. 1 = start condition detected 0 = stop condition detect ed or ddc is disabled mast ? master control bit this bit is set to initia te a master mode transf er. in master mode, the module generates a star t condition to the sda and scl lines, followed by sending the calli ng address stor ed in ddcadr. when the mast bit is cleared by nakif set (no acknowledge) or by software, the module generat es the stop conditi on to the lines after the current byte is transmitted. if an arbitration loss occurs (alif = 1), the module reverts to slave mode by clearing mast, and releasing sda and scl lines immediately. this bit is cleared by writi ng "0" to it or by reset. 1 = master mode operation 0 = slave mode operation mrw ? master read/write this bit will be tr ansmitted out as bit 0 of th e calling address when the module sets the mast bit to enter master mode. the mrw bit determines the transfer direction of the data bytes that follows. when it is "1", the module is in master receive mode. when it is "0", the module is in master transmit mode. reset clears this bit. 1 = master mode receive 0 = master mode transmit ddc12ab interface ddc registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 243 br2?br0 ? baud rate select these three bits select one of eigh t clock rates as the master clock when the module is in master mode. since this master clock is deri ved the cpu bus cl ock, the user program should not execute the wait instruction when the ddc module in master mode. this will cause the sda and scl lines to hang, as the wait instruction places the mcu in wait mode, with cpu clock is halted. these bits are cleared upon reset. (see table 16-2 . baud rate select .) table 16-2. baud rate select br2 br1 br0 baud rate 000 100k 001 50k 010 25k 011 12.5k 1 0 0 6.25k 1 0 1 3.125k 1 1 0 1.56k 1 1 1 0.78k note: cpu bus clock is external clock 4 = 6mhz ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 244 ddc12ab interface freescale semiconductor 16.6.5 ddc status register (ddcsr) rxif ? ddc receive interrupt flag this flag is set after the data rece ive register (d dcdrr) is loaded with a new received data. once the ddcdrr is l oaded with received data, no more received data can be loaded to the ddcdrr until the cpu reads the data fr om the ddcdrr to clear rxbf flag. rxif generates an interrupt request to cpu if the dien bi t in ddccr is also set. this bit is cleared by writing "0" to it or by reset; or when the den = 0. 1 = new data in data re ceive register (ddcdrr) 0 = no data received txif ? ddc transmit interrupt flag this flag is set when data in the da ta transmit register (ddcdtr) is downloaded to the output circuit, and that new data ca n be written to the ddcdtr. txif generates an interr upt request to cpu if the dien bit in ddccr is also set. this bit is cleared by writing "0 " to it or when the den = 0. 1 = data transfer completed 0 = data transfer in progress match ? ddc address match this flag is set when the received data in the data receive register (ddcdrr) is a calling address which matches with the address or its extended addresses (extad=1) specif ied in the ddcadr register. 1 = received address matches ddcadr 0 = received address does not match address: $0019 bit 7654321bit 0 read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 = unimplemented figure 16-6. ddc stat us register (ddcsr) ddc12ab interface ddc registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 245 srw ? ddc slav e read/write this bit indicates the data direction when the module is in slave mode. it is updated after t he calling address is rece ived from a master device. srw = 1 when the calling mast er is reading data from the module (slave transmit mode). srw = 0 when the master is writing data to the module (receive mode). 1 = slave mode transmit 0 = slave mode receive rxak ? ddc receive acknowledge when this bit is clear ed, it indicate s an acknowledge signal has been received after the comp letion of 8 data bits transmission on the bus. when rxak is set, it indicates no acknowledge signal has been detected at the 9th clo ck; the module will releas e the sda line for the master to generate "stop" or "repeated start" condi tion. reset sets this bit. 1 = no acknowledge signal received at 9th clock bit 0 = acknowledge signal re ceived at 9th clock bit sclif ? scl interrupt flag this flag is set when a falling edge is detected on the scl line, only if ddc1en bit is set. scli f generates an interrupt request to cpu if the sclien bit in ddccr is also set. scl if is cleared by wr iting "0" to it or when the dcc1en = 0 , or den = 0. reset clears this bit. 1 = falling edge de tected on scl line 0 = no falling edge detected on scl line txbe ? ddc transmit buffer empty this flag indicates the status of t he data transmit register (ddcdtr). when the cpu writes the data to the ddcdtr, the txbe flag will be cleared. txbe is set when ddcdtr is emptied by a transfer of its data to the output circuit. reset sets this bit. 1 = data transmit register empty 0 = data transmit register full ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 246 ddc12ab interface freescale semiconductor rxbf ? ddc rece ive buffer full this flag indicates the status of the data receive register (ddcdrr). when the cpu reads t he data from the ddcd rr, the rxbf flag will be cleared. rxbf is se t when ddcdrr is full by a transfer of data from the input circuit to t he ddcdrr. reset clears this bit. 1 = data receive register full 0 = data receive register empty 16.6.6 ddc data transm it register (ddcdtr) when the ddc module is enabled, den = 1, data written into this register depends on whether module is in master or slave mode. in slave mode, the dat a in ddcdtr will be tr ansferred to the output circuit when: the module detects a matched ca lling address (match = 1), with the calling master re questing data (srw = 1); or the previous data in the output circuit has be tr ansmitted and the receiving master returns an a cknowledge bit, indicated by a received acknowledge bit (rxak = 0). if the calling master does not return an acknowledge bit (rxak = 1), the module will release the sda line for master to generate a "stop" or "repeated start" condi tion. the data in the ddcdtr will not be transferred to the output ci rcuit until the next ca lling from a master. the transmit buffer empty flag remains cleared (txbe = 0). in master mode, the dat a in ddcdtr will be trans ferred to the output circuit when: address: $001a bit 7654321bit 0 read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 figure 16-7. ddc data tr ansmit register (ddcdtr) ddc12ab interface ddc registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 247 the module receives an ack nowledge bit (r xak = 0), after setting master transmit mode (m rw = 0), and the calling address has been transmitted; or the previous data in the output circuit has be tr ansmitted and the receiving slave retu rns an acknowledge bi t, indicated by a received acknowledge bit (rxak = 0). if the slave does not return an a cknowledge bit (rxak = 1), the master will generate a "stop" or "repeated start" condition . the data in the ddcdtr will not be transfe rred to the output circ uit. the transmit buffer empty flag remains cleared (txbe = 0). the sequence of events for slave tr ansmit and master transmit are illustrated in figure 16-9 . 16.6.7 ddc data rece ive register (ddcdrr) when the ddc module is enabled, den = 1, data in this read-only register depends on whether module is in master or slave mode. in slave mode, the data in ddcdrr is: the calling address from the ma ster when the address match flag is set (match = 1); or the last data received when match = 0. in master mode, the data in the ddcdrr is: the last data received. address: $001b bit 7654321bit 0 read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 = unimplemented figure 16-8. ddc data receive regist er (ddcdrr) ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 248 ddc12ab interface freescale semiconductor when the ddcdrr is read by the cpu, the receiv e buffer full flag is cleared (rxbf = 0), and the next received dat a is loaded to the ddcdrr. each time when new data is loaded to the ddcdrr, the rxif interrupt flag is set, indicati ng that new data is available in ddcdrr. the sequence of events for slave receive and master receive are illustrated in figure 16-9 . 16.7 programmin g considerations when the ddc module detect s an arbitration loss in master mode, it will release both sda and scl lines immediately. but if there are no further stop conditions detected, the module will hang up. therefore, it is recommended to have time -out software to re cover from such ill condition. the software can start the ti me-out counter by looking at the bb (bus busy) flag in the ddcmcr and rese t the counter on the completion of one byte tr ansmission. if a time-out occur, software can clear the den bit (dis able ddc module) to release the bus, and hence clearing the bb flag. this is the only way to clear the bb flag by software if the module hangs up due to a no stop condi tion received. the ddc can resume operation again by setting the den bit. ddc12ab interface programming considerations mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ddc12ab interface 249 figure 16-9. data transf er sequences for master/sla ve transmit/receive modes start address ack tx data1 txbe=0 mrw=0 mast=1 txif=1 txbe=1 nakif=1 mast=0 txbe=1 (a) master transmit mode (b) master receive mode (c) slave transmit mode txif=1 txbe=0 ack tx datan nak stop txif=1 txbe=1 start address ack rx data1 rxbf=0 mast=1 txbe=0 rxbf=1 rxif=1 nakif=1 mast=0 rxif=1 rxbf=1 ack rx datan nak stop 1 start address ack tx data1 txbe=1 rxbf=0 nakif=1 txbe=0 txbe=1 (d) slave receive mode txif=1 ack tx datan nak stop rxbf=1 rxif=1 match=1 srw=1 txif=1 txbe=1 0 start address ack rx data1 rxbf=1 rxif=1 rxif=1 rxbf=1 ack rx datan nak stop txbe=0 rxbf=0 rxbf=1 rxif=1 match=1 srw=0 data1 ddcdrr datan ddcdrr data1 ddcdtr data2 ddcdtr datan+2 ddcdtr data1 ddcdtr data2 ddcdtr data3 ddcdtr datan+2 ddcdtr (dummy data ddcdtr) mrw=1 data1 ddcdrr datan ddcdrr 0 1 key: shaded data packets indicate a transmit by the mcu?s ddc module ddc12ab interface data sheet mc68hc908ld64 ? rev. 3.0 250 ddc12ab interface freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 251 data sheet ? mc68hc908ld64 section 17. sync processor 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 17.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 17.5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.5.1 polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.1 hsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.2 vsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 256 17.5.1.3 composite sync polarity detect ion . . . . . . . . . . . . . . . . 256 17.5.2 sync signal counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 17.5.3 polarity controlled hout and vout outputs . . . . . . . . . . 257 17.5.4 clamp pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 17.5.5 low vertical frequency detect . . . . . . . . . . . . . . . . . . . . . 259 17.6 sync processor i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . 259 17.6.1 sync processor control & stat us register ( spcsr). . . . . 259 17.6.2 sync processor input/output control register (spiocr) . 261 17.6.3 vertical frequency registers (vfrs) . . . . . . . . . . . . . . . . . 263 17.6.4 hsync frequency registers (hfrs). . . . . . . . . . . . . . . . . . 265 17.6.5 sync processor control register 1 (spcr1). . . . . . . . . . . 267 17.6.6 h & v sync output control re gister (hvocr) . . . . . . . . . 268 17.7 system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 sync processor data sheet mc68hc908ld64 ? rev. 3.0 252 sync processor frees cale semiconductor 17.2 introduction the sync processor is designed to detect and process sync signals inside a digital monitor system ? from separated hsync and vsync inputs. after detection and the necessary polarity correction and/or sync separation, the correct ed sync signals are sent out. the mcu can also send commands to other m onitor circuitry, such as for the geometry correction and osd, using the ddc12a b and/or the iic communication channels. the block diagram of the sync processor is shown in figure 17-2 . note: all quoted timings in this section assume an internal bus frequency of 6mhz. 17.3 features features of the sync proc essor include the following: polarity detector horizontal frequency counter vertical frequency counter low vertical frequency indicator (40.7hz) polarity controlled hout and vout outputs: ? from separate hsync and vsync ? from composite syn c on hsync input pin ? from internal selectable fr ee running hsync and vsync pulses free-running hsync, vsync, de, and dclk of 4 video modes clamp pulse output to the external pre-amp chip internal schmitt trigger on hsync, and vsync input pins to improve noise immunity sync processor i/o pins mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 253 17.4 i/o pins the sync processor uses seven i/o pins, with four pins shared with standard port i/o pins and one pin shar ed with timer channel 0. the full name of the sync processor i/o pins are listed in table 17-1 . the generic pin name appear in t he text that follows. table 17-1. pin name conventions sync processor generic pin names: full mcu pin names: pin selected for sync processor function by: hsync hsync ? vsync vsync ? hout ptd3/hout houte bit in pdcr ($0069) vout ptd2/vout voute bit in pdcr ($0069) de ptd1/de dee bit in pdcr ($0069) dclk ptd0/dclk dclke bit in pdcr ($0069) clamp clamp/tch0 els0b and els0a bits in tsc0 ($0010) sync processor data sheet mc68hc908ld64 ? rev. 3.0 254 sync processor frees cale semiconductor addr.register name bit 7654321bit 0 $0040 sync processor control and status register (spcsr) read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 $0041 vertical frequency high register (vfhr) read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 $0042 vertical frequency low register (vflr) read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 $0043 hsync frequency high register (hfhr) read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 $0044 hsync frequency low register (hflr) read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 $0045 sync processor i/o control register (spiocr) read: vsyncs hsyncs coinv r r r bpor sout write: reset:000 00 $0046 sync processor control register 1 (spcr1) read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:0000 00 $003f h&v sync output control register (hvocr) read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved figure 17-1. sync processor i/o register summary sync processor functional blocks mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 255 17.5 functional blocks figure 17-2. sync pr ocessor block diagram 13-bit counter 48 a 1 b s extracted vsync a 1 b s svf comp sout vinvo vout polarity detect edge detect vpol one shot vedge internal bus clock overflow detect vof lvsie to interrupt logic 12-bit counter one shot overflow detect clk32/32.768 hsync dclk b a 1 s polarity detect hpol comp vsync extractor extracted vsync b a 1 s h/v sync, de, dclk dclk1 pulse generator svf shf clamp pulse generator clamp hout vflr vfhr hflr hfhr bpor coinv sout hover vpol vsie vsif $c00 detect lvsif hinvo hvocr[1:0] vsync 125khz 6mhz de from cgm dclkph[1:0] sync processor data sheet mc68hc908ld64 ? rev. 3.0 256 sync processor frees cale semiconductor 17.5.1 polarity detection 17.5.1.1 hsync polarity detection the hsync polarity detection circuit measures the length of high and low period of the hsync input. if the length of high is longer than l and the length of low is shorter than s , the hpol bit will be "0", indicating a negative polarity hsync in put. if the length of low is longer than l and the length of high is shorter than s , the hpol bit will be "1", indicating a positive polarity hsync input. the table below shows three possible cases for hsync polarity detection ? the conditions are selected by the hps[1:0] bits in the sync proc essor control register 1 (spcr1). 17.5.1.2 vsync polarity detection the vsync polarity detection circuit per forms a similar function as for hsync. if the length of high is l onger than 4ms and the length of low is shorter than 2ms, the vpol bit will be "0", indicating a negative polarity vsync input. if the length of low is longer t han 4ms and t he length of high is shorter than 2ms, the vpol bi t will be "1", indi cating a positive polarity vsync input. 17.5.1.3 composite sync polarity detection when a composite sync signal is t he input (comp = 1 for composite sync processing), the hpol bit = vpol bit, and the pol arity is detected using the vsync polarity detection criteria described in section 17.5.1.2 . polarity detection pulse width spcr1 ($0046) long is greater than ( l ) short is less than ( s ) hps1 hps0 7 s6 s00 3.5 s3 s1x 14 s12 s01 sync processor functional blocks mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 257 17.5.2 sync signal counters there are two counters: a 13-bit horiz ontal frequency counter to count the number of horizontal sync pulses within a 32ms or 8ms period; and a 13-bit vertical frequency counter to count the number of system clock cycles between two vertical sync pulse s. these two dat a can be read by the cpu to che ck the signal frequencies and to determine the video mode. the 13-bit vertical frequency register encompasses vertical frequency range from approximately 15hz to 128khz. due to the asynchronous timing between the incomi ng vsync signal and intern al system clock, there will be 1 count er ror on reading the vert ical frequency registers (vfrs) for the same vertical frequency. the horizontal counter counts the pul ses on hsync pin input, and is uploaded to the hsync fr equency registers (hfrs) every 32.768ms or 8.192ms. 17.5.3 polarity controll ed hout and vout outputs the processed sync signals are ou tput on hout an d vout when the corresponding bits in configuratio n register 0 ($0069) are set. the signal to these output pins depe nd on sout and comp bits (see table 17-2 ), with polarity contro lled by atpol, hinvo , and vinvo bits as shown in table 17-3 . table 17-2. sync output control sout comp sync outputs: vout and hout 1 x free-running video mode output 00 sync outputs follow sync inputs vsync and hsync respectively, with polarity correction shown in table 17-3 . 01 hout follows the composite sy nc input and vout is the extracted vsync (3 to 14 s delay to composite input), with polarity correction shown in table 17-3 . sync processor data sheet mc68hc908ld64 ? rev. 3.0 258 sync processor frees cale semiconductor when the sout bit is set, the hout output is a free-runn ing pulse. both hout and vout outputs are negativ e polarity, with frequencies selected by the h & v sync out put control regi ster (hvocr). 17.5.4 clamp pulse output when the els0b and els0a bits in t he tsc0 register are logic 0 (see table 11-3 ), a clamp signal is output on the clam p pin. this clamp pulse is triggered either on the leading edge or the trailing edge of hsync, controlled by bpor bit, wit h the polarity c ontrolled by the coinv bit. see figure 17-3 . clamp pulse output timing . figure 17-3. clamp pulse output timing table 17-3. sync output polarity atpol sout vinvo or hinvo sync outputs: vout/hout x 1 x free-running video mode output 0 0 0 same polarity as sync input 0 0 1 inverted polarity of sync input 1 0 0 negative polarity sync output 1 0 1 positive polarity sync output pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s hsync (hpol = 1) clamp (bpor = 0) clamp (bpor = 1) hsync (hpol = 0) clamp (bpor = 0) clamp (bpor = 1) sync processor sync processor i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 259 17.5.5 low vertical frequency detect logic monitors the value of the vsync frequency register (vfr), and sets the low vertical frequency flag (l vsif) when the value of vfr is higher than $c00 (frequency below 40.7hz). lvsif bit can generate an interrupt request to t he cpu when the lvsie bit is set and i-bit in the condition code re gister is "0". the lvsif bit can help the system to detect video off mode fast. 17.6 sync processor i/o registers eight registers are associ ated with the sync proce ssor, they outlined in the following sections. 17.6.1 sync processor contro l & status register (spcsr) vsie ? vsync interrupt enable when this bit is set, the vsif flag is enabled to generate an interrupt request to the cpu. when vsie is cleared, the vsif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = vsif bit set will generat e interrupt request to cpu 0 = vsif bit set does not generate interr upt request to cpu address: $0040 bit 7654321bit 0 read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 = unimplemented figure 17-4. sync processor cont rol & status register (spcsr) sync processor data sheet mc68hc908ld64 ? rev. 3.0 260 sync processor frees cale semiconductor vedge ? vsync interrupt edge select this bit specifies the triggering edge of vsync interrupt. when it is "0", the rising edge of internal vsync signal which is either from the vsync pin or extracted from the composite input signal will set vsif flag. when it is "1", t he falling edge of internal vsync signal will set vsif flag. reset clears this bit. 1 = vsif bit will be set by falling edge of vsync 0 = vsif bit will be set by rising edge of vsync vsif ? vsync interrupt flag this flag is only set by the specified edge of the internal vsync signal, which is either from the vsync input pin or extracted from the composite sync input si gnal. the triggering edge is specified by the vedge bit. vsif generat es an interrupt reques t to the cpu if the vsie bit is also set. this bit is cleared by writing a "0" to it or by a reset. 1 = a valid edge is detected on the vsync 0 = no valid vsync is detected comp ? composite sync input enable this bit is set to enable the separato r circuit which extracts the vsync pulse from the composite sync inpu t on hsync. the extracted vsync signal is used as it were from the vsync input. reset clears this bit. 1 = composite sync input enabled 0 = composite sync input disabled vinvo ? vout signal polarity this bit, toget her with the atpol bit in spcr1 controls the output polarity of the vout signal (see table 17-4 ). hinvo ? hout signal polarity this bit, toget her with the atpol bit in spcr1 controls the output polarity of the hout signal (see table 17-4 ). sync processor sync processor i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 261 vpol ? vsync input polarity this bit indicates the polarity of the vsync input, or t he extracted vsync from a composite sync input (comp=1). reset clears this bit. 1 = vsync is positive polarity 0 = vsync is negative polarity hpol ? hsync input polarity this bit indicates the polarity of the hsync input. thi s bit equals the vpol bit when the co mp bit is set. re set clears this bit. 1 = hsync is positive polarity 0 = hsync is negative polarity 17.6.2 sync processor input/output control register (spiocr) vsyncs ? vsync input state this read-only bit reflects the l ogical state of the vsync input. hsyncs ? hsync input state this read-only bit reflects the l ogical state of the hsync input. table 17-4. atpol, vinvo, and hinvo setting atpol vinvo / hinvo sync outputs: vout/hout 0 0 same polarity as sync input 0 1 inverted polarity of sync input 1 0 negative polarity sync output 1 1 positive polarity sync output address: $0045 bit 7654321bit 0 read: vsyncs hsyncs coinv r r r bpor sout write: reset:000 00 = unimplemented r = reserved figure 17-5. sync processor input/output contro l register (spiocr) sync processor data sheet mc68hc908ld64 ? rev. 3.0 262 sync processor frees cale semiconductor coinv ? clamp output invert this bit is set to inve rt the clamp pulse out put to negative. reset clears this bit. 1 = clamp output is se t for negative pulses 0 = clamp output is se t for positive pulses bpor ? back porch this bit defines the tri ggering edge of the clamp pu lse output relative to the hsync input. reset clears this bit. 1 = clamp pulse is generated on the trailing edge of hsync 0 = clamp pulse is generated on the leading edge of hsync sout ? sync output enable this bit will select the output signals for the vout and hout pins and generate the de and dclk signals to the pins . reset clears this bit. 1 = vout, hout, de, and dclk ou tputs are internally generated free-running timing pulses with frequenc ies determined by hvcor[1:0] bits in hvcor and cgm values. 0 = vout and hout outputs are processed vsync and hsync inputs respectively and de and dclk are hold as logic low. sync processor sync processor i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 263 17.6.3 vertical fr equency registers (vfrs) this register pair c ontains the 13-bit vertical frequency count value, an overflow bit, and the clamp pulse width selection bits. vf[12:0] ? vertical frame frequency this read-only 13-bit contains info rmation of the vertical frame frequency. an internal 13-bit counter counts the number of 8 s periods between two vsync pulses. the most significant 5 bits of the counted value is transferred to the hi gh byte register, and the least significant 8 bits is transferred to an interm ediate buffer. when the high byte register is read, the 8-bit counted val ue stored in the intermediate buffer will be uploaded to the lo w byte register. therefore, user program must read t he high byte register first, then low byte register in order to get the comple te counted value of one vertical frame. if the counter overfl ows, the overflow flag, vof, will be set, indicating the counter value st ored in the vfrs is meaningless. the data corresponds to th e period of one vertical frame. this register can be read to determine if t he frame frequency is valid, and to determine the video mode. address: $0041 bit 7654321bit 0 read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 figure 17-6. vertical frequency high register address: $0042 bit 7654321bit 0 read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 = unimplemented figure 17-7. vertical frequency low register sync processor data sheet mc68hc908ld64 ? rev. 3.0 264 sync processor frees cale semiconductor the frame frequency is calculated by: table 17-5 shows examples for the vert ical frequency regi ster, all vfr numbers are in hexadecimal. vof ? vertical frequen cy counter overflow this read-only bit is set when an over flow has occurred on the 13-bit vertical frequency counter. reset clears this bit, and will be updated every vertical frame. an overflow occurs when the period of vsync frame exceeds 64.768ms (a vertical frame fr equency lower than 15.258hz). 1 = a vertical frequency count er overflow has occurred 0 = no vertical frequency counter overflow has occurred table 17-5. sample ve rtical frame frequencies vfr max freq. min freq. vfr max freq. min freq. $02a0 186.20 hz 185.70 hz $0780 65.10 hz 65.00 hz $03c0 130.34 hz 130.07 hz $0823 60.04 hz 59.98 hz $03c1 130.21 hz 129.94 hz $0824 60.01 hz 59.95 hz $03c2 130.07 hz 129.80 hz $0825 59.98 hz 59.92 hz $04e2 100.08 hz 99.92 hz $09c4 50.02 hz 49.98 hz $04e3 100.00 hz 99.84 hz $09c5 50.00 hz 49.96 hz $04e4 99.92 hz 99.76 hz $09c6 49.98 hz 49.94 hz $06f9 70.07 hz 69.99 hz $1ffd 15.266 hz 15.262 hz $06fa 70.03 hz 69.95 hz $1ffe 15.264 hz 15.260 hz $06fb 69.99 hz 69.91 hz $1fff 15.262 hz 15.258 hz vertical frame frequency 1 vfr 1 48 t cyc --------------- ----------------- ------------------ - = 1 vfr 1 8 s ------------------ ------------------- - = for internal bus clock of 6mhz sync processor sync processor i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 265 cpw[1:0] ? clamp pulse width the cpw1 and cpw0 bits are used to select the output clamp pulse width. reset clears these bits, se lecting a default clamp pulse width between 0.33 s and 0.375 s. these bits al ways read as zeros. 17.6.4 hsync freque ncy registers (hfrs) this register pair contains the 13-bit hsyn c frequency count value and an overflow bit. table 17-6. clamp pulse width cpw1 cpw0 clamp pulse width 0 0 0.33 s to 0.375 s 010.5 s to 0.542 s 1 0 0.75 s to 0.792 s 112 s to 2.042 s address: $0043 bit 7654321bit 0 read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 figure 17-8. hsync fr equency high register address: $0044 bit 7654321bit 0 read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 = unimplemented figure 17-9. hsync frequency low register sync processor data sheet mc68hc908ld64 ? rev. 3.0 266 sync processor frees cale semiconductor hfh[7:0], hfl[4:0] ? ho rizontal line frequency this read-only 13-bit cont ains the number of ho rizontal lines in a 32ms window. an internal 13-bit counter counts the hsync pulses within a 32ms window in every 32.7 68ms period. if the fshf bit in spcr1 is set, only the most 11-bi ts (hfh[7:0] & hfl[4:2]) will be updated by the counter. thus, providi ng a hsync pulse count in a 8ms window in every 8.192ms. the most significant 8 bits of counted value is tr ansferred to the high byte register, and the l east significant 5 bits is transferred to an intermediate buffer. when the high byte regist er is read, the 5-bit counted value stored in the interm ediate buffer will be uploaded to the low byte register. therefore, user the program must read the high byte register first then low byte regist er in order to get the complete counted value of hsync pulses. if t he counter overflows, the overflow flag, hover, will be set, indicating the num ber of hsync pulses in 32ms are more than 8191 (2 13 ?1), i.e. a hsync frequency greater than 256khz. for the 32ms window, the hfhr and hflr are such that the frequency step unit in the 5-bit of hflr is 0.03125khz, and the step unit in the 8-bit hfhr is 1khz. therefore, the hsync frequency can be easily calculated by: hover ? hsync frequen cy counter overflow this read-only bit is set when an over flow has occurred on the 13-bit hsync frequency counter. reset clear s this bit, and will be updated every count period. an overflow occurs when the num ber hsync pulses exceed 8191, a hsync frequency great er than 256khz. 1 = a hsync frequency counter overflow has occurred 0 = no hsync frequency coun ter overflow has occurred hsync frequency = [ hfh + ( hfl 0.03125)] khz where: hfh is the value of hfh[7:0] hfl is the value of hfl[4:0] sync processor sync processor i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 267 17.6.5 sync processor cont rol register 1 (spcr1) lvsie ? low vsync interrupt enable when this bit is set, the lvsif fl ag is enabled to generate an interrupt request to the cpu. w hen lvsie is cleared, the lvsif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = low vsync interrupt enabled 0 = low vsync interrupt disabled lvsif ? low vsync interrupt flag this read-only bit is set when the va lue of vfr is higher than $c00 (vertical frame frequency below 40.7hz). lvsif generates an interrupt request to the cpu if the lvsi e is also set. this bit is cleared by writing a "0" to it or reset. 1 = vertical frequency is below 40.7hz 0 = vertical frequency is higher than 40.7hz hps[1:0] ? hsync input detecti on pulse width these two bits control the detecti on pulse width of hsync input. reset clears these two bits, sett ing a default middle frequency of hsync input. address: $0046 bit 7654321bit 0 read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:0000 00 = unimplemented r = reserved figure 17-10. sync processor cont rol register 1 (spcr1) table 17-7. hsync polarity detection pulse width hps1 hps0 polarity detection pulse width 0 0 long > 7 s and short < 6 s 1 x long > 3.5 s and short < 3 s 0 1 long > 14 s and short < 12 s sync processor data sheet mc68hc908ld64 ? rev. 3.0 268 sync processor frees cale semiconductor atpol ? auto polarity this bit, toget her with the vinvo or hinvo bits in spcsr controls the output polarity of t he vout or hout signals respectively. reset clears this bit (see table 17-8 ). fshf ? fast horizontal frequency count this bit is set to s horten the measurement cycle of the horizontal frequency. if it is set, only hfh[7:0] and hfl[4:2] will be updated by the hsync counter, pr oviding a count in a 8ms window in every 8.192ms, with hfl[1:0] reading as zeros. therefore, user can determine the horizontal frequency c hange within 8.192ms to protect critical circuitry. re set clears this bit. 1 = number of hsync pulse s is counted in an 8ms window 0 = number of hsync pulses is counted in a 32ms window 17.6.6 h & v sync output control register (hvocr) table 17-8. atpol, vinvo, and hinvo setting atpol vinvo / hinvo sync outputs: vout/hout 0 0 same polarity as sync input 0 1 inverted polarity of sync input 1 0 negative polarity sync output 1 1 positive polarity sync output address: $003f bit 7654321bit 0 read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved figure 17-11. h&v sy nc output control register (hvocr) sync processor system operation mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor sync processor 269 dclkph[1:0] ? dclk output phase adjustment these two bits are programmed to adjust the dclk output phase. each increment adds app roximately 2 to 3ns delay to the dclk output. hvocr[1:0] ? free runni ng video mode select bits these two bits together with mul[ 7:4] and vrs[7:4] in cgm?s pll programming register determine the frequencies of the internal generated free-running si gnals for output to hout, vout, de, and dclk pins, when the sout bit is set in the syn c processor i/o control register. these two bits determine the presca ler of pll reference clock in the cgm module. when hvoc r[1:0]=11, the prescaler is 2; for other values, t he prescaler is 3. reset clears these bits, setting a default horizontal frequency of 31.25khz and a ve rtical frequency of 60hz, a video mode of 640 480. (see section 8. cl ock generator module (cgm) .) 17.7 system operation this sync processor is designed to a ssist in determining the video mode of incoming hsync and vsy nc of various frequenc ies and polarities, and dpms modes. in the dpms standard, a no sync pulses definition can be detected when the value of the hsync frequency register (the number of hsync pulses) is less than one or when the vof bit is set. since the hsync frequency register is updated repeatedly in every 32.768ms, and a valid vsync must have a frequen cy greater than 40.7hz, a valid vsync pul se will arrive withi n the 32.768ms window. therefore, the user should read t he hsync frequency register every 32.768ms to determine the presence of hsync and/or vsync pulses. table 17-9. free-runn ing hsout, vsout, de, and dclk settings hvocr[1:0] mul[7:4] vrs[7:4] hout frequency vout frequency dclk frequency de video mode 00 3 3 31.45khz 59.91hz 24mhz vga 640 480 01 5 3 37.87khz 60.31hz 40mhz svga 800 600 10 8 6 48.37khz 60.31hz 64mhz xga 1024 768 11 9 9 64.32khz 60.00hz 108mhz sxga 1280 1024 sync processor data sheet mc68hc908ld64 ? rev. 3.0 270 sync processor frees cale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 271 data sheet ? mc68hc908ld64 section 18. on-scr een display (osd) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.4 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.5 osd flash font memory map . . . . . . . . . . . . . . . . . . . . . . . 275 18.6 osd screen memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 18.7 osd module i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . .277 18.7.1 osd control register (osdcr) . . . . . . . . . . . . . . . . . . . . 277 18.7.2 osd status register (osdsr) . . . . . . . . . . . . . . . . . . . . . 278 18.7.3 osd data registers (osddrh: osddrl) . . . . . . . . . . . . 279 18.7.4 osd row address register (osdr ar) . . . . . . . . . . . . . . 280 18.7.5 osd column address register (osdcar). . . . . . . . . . . . 280 18.7.6 osd flash even high byte write buffer (osdehbuf) . 281 18.8 osd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.8.1 osd display registers (attri bute and code re gisters) . . . 282 18.8.2 row attribute registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.8.3 control, window, and pattern registers . . . . . . . . . . . . . . 283 18.8.3.1 window register s 1, 2, 3, 4 . . . . . . . . . . . . . . . . . . . . . . 284 18.8.3.2 vertical delay control register . . . . . . . . . . . . . . . . . . . 285 18.8.3.3 horizontal delay c ontrol register . . . . . . . . . . . . . . . . . 286 18.8.3.4 character height control register . . . . . . . . . . . . . . . . . 286 18.8.3.5 frame control regist ers . . . . . . . . . . . . . . . . . . . . . . . . 288 on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 272 on-screen display (osd) freescale semiconductor 18.2 introduction this section describes the on-screen displa y (osd) module. this module includes a 15 row 30 column display wi ndow and video pattern generator. 18.3 features features of the on-scree n display module include: up to 384 fonts: 12 16 or 16 16 resolution: up to 2048 dots/line scan lines per fram e: up to 2048 lines fully programmable disp lay character array of 15 rows by 30 columns eight selections of co lor for menu windows and fonts row to row spacing control four programmable background windows window shadowing with program mable width, height, and color programmable vertical and horiz ontal positioning for display center full screen pattern output of free-running vga, svga, xga, sxga timing from sy nc processor module double character height and double character width on-screen display (osd) system overview mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 273 18.4 system overview the osd module has a full screen memo ry architecture. refresh is done by the built-in synchronous circuitry. the full scr een display data can be updated through writing row, column, and data buffers. thus, the display data can be updated randomly afterward. figure 18-2 shows the block diagram of the osd module. addr.register name bit 7654321bit 0 $0060 osd control register (osdcr) read: osdmen r osdrst clkinv clkph1 clkph0 halfclk osdien write: reset:0 000000 $0061 osd status register (osdsr) read: wrdy dendif write: 0 reset: 1 0 $0062 osd data register low (osddrl) read: osdd7 osdd6 osdd5 osdd4 osdd3 osdd2 osdd1 osdd0 write: reset: unaffected by reset $0063 osd data register high (osddrh) read: osdd15 osdd14 osdd13 osdd12 osdd11 osdd10 osdd9 osdd8 write: reset: unaffected by reset $0064 osd row address register (osdrar) read: rowa3 rowa2 rowa1 rowa0 write: reset: 0000 $0065 osd column address register (osdcar) read: cola4 cola3 cola2 cola1 cola0 write: reset: 00000 $0066 osd flash even high byte write buffer (osdehbuf) read: dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 write: reset: unaffected by reset = unimplemented r = reserved figure 18-1. on-scr een display i/o register summary on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 274 on-screen display (osd) freescale semiconductor figure 18-2. osd block diagram user program must writ e the row and column addresses to the row and column address registers, then write the code and attributes to the 16-bit osd data register to co mplete one display char acter or symbol update. the wrdy bit will then be set to acknowl edge that the data has been updated to the addressed di splay ram. this pr ocess is repeated for other updates. row and column address generator 16 16 384 fonts flash memory pvsync phsync row and column code shift register frame attribute pattern generator osdr osdg osdb fbkg output logic control pclk address clock generator row attribute latches 16 row 32 column attribute and code display ram internal bus row and column address and data buffers control logic osdmen $0062 $0063 $0064 $0065 $0060 bit7 on-screen display (osd) osd flash font memory map mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 275 18.5 osd flash font memory map the 12k-byte flash memory from $1000 to $3fff is for osd font storage. this osd font memory stor es up to 384 fonts, with each font made up of 16 lines by 16 bits, i.e. 32 memory locations. the osd fonts memory can be accessed by cpu when the osdmen bi t in the osd control register is clear. see 18.7.6 osd flash even high byte write buffer (osdehbuf) for how to program the osd font memory. figure 18-3. memory map of osd flash fonts 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dot 16 lines 16 lines $0000 $0001 $0002 $017f even byte odd byte $1000 $1002 $1004 $1006 $1008 $100a $100c $100e $1010 $1012 $1014 $1016 $1018 $101a $101c $101e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? $1001 $1003 $1005 $1007 $1009 $100b $100d $100f $1011 $1013 $1015 $1017 $1019 $101b $101d $101f $1020 $1022 $1024 $1026 $1028 $102a $102c $102e $1030 $1032 $1034 $1036 $1038 $103a $103c $103e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? $1021 $1023 $1025 $1027 $1029 $102b $102d $102f $1031 $1033 $1035 $1037 $1039 $103b $103d $103f $3fe0 $3fe2 $3fe4 $3fe6 $3fe8 $3fea $3fec $3fee $3ff0 $3ff2 $3ff4 $3ff6 $3ff8 $3ffa $3ffc $3ffe ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? $3fe1 $3fe3 $3fe5 $3fe7 $3fe9 $3feb $3fed $3fef $3ff1 $3ff3 $3ff5 $3ff7 $3ff9 $3ffb $3ffd $3fff font memory address character code on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 276 on-screen display (osd) freescale semiconductor 18.6 osd screen memory map the osd operating screen is mapped to a 1k-byte ram array from $0800 to $0bff. the array is organized as 16 rows by 32 columns, with two bytes (16-bit) for eac h row-column location. figure 18-4 shows the osd screen memory map. figure 18-4. memory map of osd registers the area covering ro w0-column0 and row14-co lumn29 are called the active display registers. each 16- bit display register defines the character to be displayed, with an character code (chara cter from font memory) and an attribute code for that character. column30 of each row is the attribute register for the entir e row. row15 registers (not memory mapped) are used for contro l, window, and pattern for the entire osd screen. see 18.8 osd registers for register definitions. the cpu have direct access to the all screen memory registers ($0800 to $0bff) when the osdmen bit in the osd cont rol register is clear. when the osd circuitry is displa ying the characters (osdmen=1), updates to display is by indirectly writing to these registers. the osd data registers, row regist er, column register ar e used for this purpose. see 18.7.3 osd data regi sters (osddrh:osddrl) , 18.7.4 osd row address register (osdrar) , and 18.7.5 osd column address register (osdcar) . a c a c a c a c a c a c 0 $840 1 $87f ? $880 2 $8bf ? $8c0 3 $8ff ? $900 4 $93f ? $9c0 7 $9ff ? $a00 8 $a3f ? $980 6 $9bf ? $940 5 $97f ? $a40 9 $a7f ? $ac0 11 $aff ? $a80 10 $abf ? $b00 12 $b3f ? $b40 13 $b7f ? $b80 14 $bbf ? not mapped 15 $800 $801 $802 $803 $804 $805 $806 $807 $838 0 1 2 3 28 29 30 31 a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c a c $839 $83a $83b $83c $83d $83e $83f display registers control, window, and pattern registers row attribute registers row column display ram address a = character attribute c = character code on-screen display (osd) osd module i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 277 18.7 osd module i/o registers seven registers are associated with the osd module, they outlined in the following sections. 18.7.1 osd contro l register (osdcr) osdmen ? osd me mory enable when this bit is clear, the os d ram and font flash memory is directly under cpu access. when o sdmen is set, osd circuitry has read control over the osd ra m and font flash memory for displaying the contents; cpu access is indirect, by writing to address and data buffers. the osdmen bi t should be clear ed while no osd are displaying. rese t clear this bit. 1 = osd ram and font flash is under osd circuitry access 0 = osd ram a nd font flash is dire ctly under cpu access osdrst ? osd module reset setting this bit resets the entire osd logic and row15 registers (row1 to row14 registers ar e unaffected), and holds the osd in the reset state. the input pclk clock is prevented from entering the osd module to reduce pow er consumption. reset clear this bit. 1 = reset osd logic and row15 registers 0 = no effect clkinv ? pixel clock inversion this bit is set to invert the pclk input of osd. reset clears this bit. 1 = pclk input inverted 0 = pclk input not inverted address: $0060 bit 76543210 read: osdmen r osdrst clkinv clkph1 clkph0 halfclk osdien write: reset:0 000000 figure 18-5. osd cont rol register (osdcr) on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 278 on-screen display (osd) freescale semiconductor clkph[1:0] ? pixel cl ock phase adjustment these two bits adjust th e pixel clock phase to the osd module. thus the osdr, osdg , and osdb outputs can be in phase with video signals. reset clears all these bits. halfclk ? half freq uency of pixel clock this bit is set to divi de the incoming pixel clo ck by two as the osd display clock. rese t clears this bit. 1 = osd module display cl ock is pclk divided-by-2 0 = osd module display cl ock is pclk divided-by-1 osdien ? osd interrupt enable this bit enable osd interrupt when dendif in the osd status register is set. reset clear this bit. 1 = dendif bit set w ill generate interr upt request to cpu 0 = dendif bit set w ill not generate inte rrupt request to cpu 18.7.2 osd status register (osdsr) wrdy ? osd buffer write ready this bit is set when the osd data regist ers, $0062 and $0063, are ready to be loaded with new data. the wrdy is cleared after the cpu writes to the low byte register , $0062. it becomes set again when the osd circuitry has transferred the c ontent of data r egisters to the display ram. reset sets this bit. 1 = osd data buffers ready for new data 0 = osd data buffers busy address: $0061 bit 76543210 read: wrdy dendif write: 0 reset: 1 0 = unimplemented figure 18-6. osd stat us register (osdsr) on-screen display (osd) osd module i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 279 dendif ? osd display end interrupt flag this bit is set when t he osd has finished the ro w15 display; it is cleared by writing a logi c 0 to it. the dendif bit is des igned for user program to update the osd ram while not di splaying osd. reset clears this bit. 1 = osd has finished the row15 display 0 = no effect 18.7.3 osd data re gisters (osddrh:osddrl) osdd[15:0] ? osd ram 16-bit data buffer while osd circuitry is displaying data from the display ram, update the display ram (locat ion specified by the row and column address registers, osdrar and osdcar) by writing da ta to the high byte register (osddrh) follow ed by the low byte r egister (osddrl). after writing to the osddrl, the osd buffer write re ady bit (wrdy) will be cleared. wrdy becomes set again when the osd circuitry has transferred the content of the osd da ta registers to the display ram. reset has no effect on these bits. (see 18.6 osd screen memory map .) address: $0063 bit 76543210 read: osdd15 osdd14 osdd13 osdd12 osdd11 osdd10 osdd9 osdd8 write: reset: unaffected by reset figure 18-7. osd data register high (osddrh) address: $0062 bit 76543210 read: osdd7 osdd6 osdd5 osdd4 osdd3 osdd2 osdd1 osdd0 write: reset: unaffected by reset figure 18-8. osd data register low (osddrl) on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 280 on-screen display (osd) freescale semiconductor 18.7.4 osd row addr ess register (osdrar) rowa[3:0] ? osd ram row address these bits define the row address of the osd ram. together with the column address, the row-column addr ess defines the location in the osd screen memory where data is to be transferred from the data buffers (osd data registers). data is transferred w hen the high byte data register is writt en ($0063). reset clears these bits to zero. (see 18.6 osd screen memory map .) 18.7.5 osd column ad dress register (osdcar) cola[4:0] ? osd ram column address these bits define the column addres s of the osd ram. together with the row address, the row-column addr ess defines the location in the osd screen memory where data is to be transferred from the data buffers (osd data registers). data is transferred w hen the high byte data register is writt en ($0063). reset clears these bits to zero. (see 18.6 osd screen memory map .) address: $0064 bit 76543210 read: rowa3 rowa2 rowa1 rowa0 write: reset: 0000 figure 18-9. osd row ad dress register (osdrar) address: $0065 bit 76543210 read: cola4 cola3 cola2 cola1 cola0 write: reset: 00000 figure 18-10. osd column address register (osdcar) on-screen display (osd) osd module i/o registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 281 18.7.6 osd flash even high byte write buffer (osdehbuf) dot[15:8] ? osd flash even high byte buffer these bits define the even byte for a single line of os d font, to be programmed to the osd flash memo ry. reset has no effect on these bits. figure 18-12 shows an example of an osd font. figure 18-12. osd fon t even byte buffer the osdehbuf register is a buffer for temporarily storing the even byte (or high byte) of an osd font line to be programmed to the osd flash memory. a 16-bit osd font line is programmed by writing the even byte to osdehbuf, followed by a flash programming routine to the odd byte in the font memory. program ming the odd byte will automatic program the even byte. see 18.5 osd flash fo nt memory map for osd font memory map and section 4. flash memory on flash programming. address: $0066 bit 76543210 read: dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 write: reset: unaffected by reset figure 18-11. osd flash even high byte write buffer (osdehbuf) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dot 16 lines even byte odd byte $1000 $1002 $1004 $1006 $1008 $100a $100c $100e $1010 $1012 $1014 $1016 $1018 $101a $101c $101e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? $1001 $1003 $1005 $1007 $1009 $100b $100d $100f $1011 $1013 $1015 $1017 $1019 $101b $101d $101f font memory address osdehbuf dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 282 on-screen display (osd) freescale semiconductor 18.8 osd registers the following sections define the osd registers for display control as illustrated in figure 18-4 . memory map of osd registers . 18.8.1 osd display registers (attribute and code registers) the osd active display registers consist of 450 attribute and code registers in a 15 row by 30 column matrix. these registers are memory mapped to ram location s as illustrated in figure 18-4 . when osdmen=0 (not displaying), cpu has direct access to these registers by reading/writing th e ram locations. when osdmen=1 (displaying), cpu access t hese registers indirectly by writing to the osd data registers, row regist er and column register. each attribute and code register affects one disp lay character. row 0?14, column 0?29: craddr ? character address these bits form an address to select one of the 384 characters/symbols available fr om the flash font memory. bgr, bgg, bgb ? character background color these bits define the color of the background of the associated character/symbol. when all three bi ts are clear, no background will be shown. therefore, seven backg round colors can be selected. fss ? font size this bit will determine the font size of the associated character/symbol. reset clears this bit. 1 = the font size is 12 16 (dot13 to dot2) 0 = the font size is 16 16 r, g, b ? character color these bits define the color of the associated character/symbol. bgr 15 bgg 14 bgb 13 fss 12 r 11 g 10 b 9 876543210 craddr character attribute character code on-screen display (osd) osd registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 283 18.8.2 row attr ibute registers the 15 row attribute registers are at column 30 of the display rows. these registers are memory mapped to ram locations as illustrated in figure 18-4 . when osdmen=0 (not displaying), cpu has direct access to these registers by reading/writing th e ram locations. when osdmen=1 (displaying), cpu access t hese registers indirectly by writing to the osd data registers, row regist er and column register. each row attribute register affe cts characters of a display row. row 0?14, column 30: ren ? row enable set this bit to enable osd circuitry to displa y the current row of characters. this bit should be cleared when display ram is accessed directly by the cpu and when the row points to a font that is to be updated in the flash font memory. 1 = enable display for this row 0 = disable display for this row chs ? character height set this bit to display double he ight characters for this row. 1 = display characters as double height for this row 0 = display characters as normal height for this row cws ? character width set this bit to display double wi dth characters for this row. 1 = display characters as double width for this row 0 = display characters as normal width for this row 18.8.3 control, window , and pattern registers row-15 registers are fo r window, pattern, and mi scellaneous control of the entire osd screen. these registers ar e not memory mapped to ram locations. cpu acce ss these registers by wr iting to the osd data registers, row register and column register. 15 14 13 12 11 10 9 8 7 6 5 4 3 ren 2 chs 1 cws 0 on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 284 on-screen display (osd) freescale semiconductor 18.8.3.1 window regist ers 1, 2, 3, 4 four background windows are available, with each window controlled by a set of three r egisters in row 15. window 1 has the highest priority, and window 4 the least. if window over-lapping occurs, the hi gher priority window will cover the lower one, and the higher priori ty color will take ov er on the overlapped window area. if the row/column start address is greater than the end address, that window will not be displayed. row 15, column 0, 3, 6, 9: row 15, column 1, 4, 7, 10: row 15, column 2, 5, 6, 11: wen ? background window enable set this bit to enable background window generation 1 = enable background window 0 = disable background window row 15 0123 column 4567891011 window 1 registers window 2 registers w indow 3 registers window 4 registers 76543210 row start address row end address msb lsb msb lsb 15 14 13 12 11 10 9 8 76543210 column start address msb lsb wen w_shd 15 14 13 12 11 10 9 8 76543210 column end address msb lsb rb g 15 14 13 12 11 10 9 8 on-screen display (osd) osd registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 285 w_shd ? shadow on window set this bit to activate the wi ndow shadowing. when the window is active, the right m pixels and lower n horizontal scan lines will output shadowing. the m, n, and color of window shadow is defined in the frame control registers located at row 15, column 16, 17, 18, and 19. see 18.8.3.5 frame control registers for details. 1 = background wi ndow shadow enabled 0 = background window shadow disabled r, g, b ? background window color these bits define the colo r of the background window. 18.8.3.2 vertical dela y control register row 15, column 12: vertd ?tvertical delay these bits define the vertical sta rting position. the 8-bit gives 256 steps, with each step increment of fo ur horizontal lines for each field. its value cannot be zero at any time. in order to avoid screen misalignment, the value of vertd is decided by the last osd line not over the next leadi ng edge of pvsync. window area m and n are defined in the frame control registers located at row 15, column 16 and 17. column start address row start address row end address column end address n m shadow n m 76543210 vertd msb lsb 15 14 13 12 11 10 9 8 on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 286 on-screen display (osd) freescale semiconductor 18.8.3.3 horizontal delay control register row 15, column 13: hord ? horizontal delay these bits define th e horizontal star ting position for character display. the 8-bit gives 256 steps, with each step increment of six dots shift to the right on the monito r screen. the maximum value of hord is decided by the rightmost characte r not exceeding the next leading edge of phsync. 18.8.3.4 character heig ht control register this register c ontrols the height of all displayed characters. row 15, column 14: ch[3:0] ? expand characters by brm algorithm these bits expand the 16-line char acters using the binary rate multiplier (brm) algorithm. see figure 18-13 for some examples. ch[5:4] ? display char acter height select these two bits define the final height for the di splay characters. see figure 18-14 for illustration. 76543210 hord msb lsb 15 14 13 12 11 10 9 8 ch5:ch4 character display size 00 or 01 display size is same size as expanded font by ch[3:0]. the default value is 00. 10 display size is double size of expanded font by ch[3:0]. 11 display size is triple size of expanded font by ch[3:0]. 76543210 ch2 ch0 ch1 ch5 ch4 ch3 15 14 13 12 11 10 9 8 on-screen display (osd) osd registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 287 note: to avoid undesirable on- screen displays, such as jittering and characters wrapping to the top, care should be taken when implementing character height expansion and vertical starting position ? ensure the last line of row14 does not exceed the pvsync pulse of the next frame. figure 18-13. character font matrix height expansi on by ch[3:0] figure 18-14. display character height 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 lines ch[3:0] = $6 22 lines ch[3:0] = $9 25 lines ch[3:0] = $f 31 lines characters height expanded by 4-bit brm character in font memory ch[3:0] = $0 12 16 matrix ch[5:4] = 0:0 or 0:1 1 x 2 x 3 x ch[5:4] = 1:0 ch[5:4] = 1:1 32 to 62 lines 16 to 31 lines 48 to 93 lines on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 288 on-screen display (osd) freescale semiconductor 18.8.3.5 frame control registers row 15, column 15: osd_en ? osd enable set this bit to enable the osd module output pins , osdr, osdg, osdb, and fbkg. when osd_ en is clear, all osd output pins are high impedance. this bi t is cleared after a po r, reset, or when osdrst bit (bit-5 in osd control register) is set. 1 = osd output pins: osdr, osdg, osdb, fbkg enabled 0 = osd output pins hel d at high impedance hpol ? horizontal sync polarity this bit selects the polar ity of the incoming horizontal syn c signal on phsync pin. if sync signal is negative polarity, clear this bit. if sync signal is positive polarity, set this bit. this bit is clea red after a por, reset, or when osdrst bit is set. 1 = set for positive horizontal sync signal 0 = clear for negative horizontal sync vpol ? vertical sync polarity this bit selects the polarity of t he incoming vertical sync signal on pvsync pin. if sync signal is negative polarity, clear this bit. if sync signal is positive polarity, set this bit. this bit is clea red after a por, reset, or when osdrst bit is set. 1 = set for positive vertical sync signal 0 = clear for negative vertical sync 76543210 hpol vpol osd_en 15 14 13 12 11 10 9 8 on-screen display (osd) osd registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 289 row 15, column 16 and 17 registers c ontrol the width and height of the shadow windows. row 15, column 16: wwx1, wwx0 ? shadow window width control bits these bits selects the width, m, for the respective enabled shadow window; where x is the window number. table 18-1. shadow width setting wwx1:wwx0 shadow width m (unit in pixels) 00 2 01 4 10 6 11 8 window area n m shadow n m 76543210 ww20 ww10 ww11 ww41 ww40 ww31 ww30 ww21 15 14 13 12 11 10 9 8 on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 290 on-screen display (osd) freescale semiconductor row 15, column 17: whx1, whx0 ? shadow windo w height control bits these bits selects the width, n, for the respective enabled shadow window; where x is the window number. row 15, column 18 and 19 registers control the color of the shadow windows. row 15, column 18: row 15, column 19: r x , g x , b x ? shadow window color these bits define the color of the correspondi ng shadow window; where x is the window number table 18-2. shadow width setting wh41:wh40 shadow height n (unit in lines) 00 2 01 4 10 6 11 8 76543210 wh20 wh10 wh11 wh41 wh40 wh31 wh30 wh21 15 14 13 12 11 10 9 8 76543210 r 2 b 2 g 2 r 1 g 1 b 1 15 14 13 12 11 10 9 8 76543210 r 4 b 4 g 4 r 3 g 3 b 3 15 14 13 12 11 10 9 8 on-screen display (osd) osd registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor on- screen display (osd) 291 note: the width of bottom side shadowing is counted in numbers of columns and is aligned with the character width (12 dot s or 16 dots) of the following row. therefore it is possible to have misalignment of this shadowing while different character formats are used by the last row inside the window and first row outside the win dow. the window shadowing width of row 14 is deter mined by number of columns of window times 12 dots. row 15, column 20: rspace ? row spacing these bits define the spacing between the display rows, in units of horizontal scan lines. due to the non-uniform expansion of the brm algorithm used for character height c ontrol, this register is normally used for maintaining a constant osd menu height for different display modes, instead of adjust ing the character height s. the default value is 0, i.e. no extra lines inserted between. row 15, column 21: pge ? screen video pattern enable set this bit to enable the free-r unning full-screen video pattern. reset clears this bit. 1 = screen video pattern enabled 0 = screen video pattern disabled pgr, pgg, pgb ? scr een video pattern color these bits define the color of the free-running full-screen video pattern. 76543210 rspace msb lsb 15 14 13 12 11 10 9 8 76543210 pgr pgb pgg pge 15 14 13 12 11 10 9 8 on-screen display (osd) data sheet mc68hc908ld64 ? rev. 3.0 292 on-screen display (osd) freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 293 data sheet ? mc68hc908ld64 section 19. input/output (i/o) ports 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 19.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 298 19.3.3 port a options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 19.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 19.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 301 19.4.3 port b options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 19.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.3 port c options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.6.3 port d options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 19.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.7.3 port e options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 294 input/output (i/o) ports freescale semiconductor 19.2 introduction thirty-nine (39) bidirecti onal input-output (i/o) pins form five parallel ports. all i/o pins are progr ammable as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o ports do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 19-1. port i/o register summary input/output (i/o) ports introduction mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 295 $0006 data direction register c (ddrc) read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $004f keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0068 port-e control register (pecr) read: r usbds4e usbds3e usbds2e usbds1e write: reset: 0000 $0069 port-d control register (pdcr) read: iicdate iicscle ddcdate ddcscle houte voute dee dclke write: reset:00000000 $0078 pwm control register (pwmcr) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented figure 19-1. port i/o re gister summary (continued) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 296 input/output (i/o) ports freescale semiconductor table 19-1. port contro l register bits summary port bit ddr module control pin module register control bit a 0 ddra0 kbi kbier $004f kbie0 pta0/kbi0 1 ddra1 kbie1 pta1/kbi1 2 ddra2 kbie2 pta2/kbi2 3 ddra3 kbie3 pta3/kbi3 4 ddra4 kbie4 pta4/kbi4 5 ddra5 kbie5 pta5/kbi5 6 ddra6 kbie6 pta6/kbi6 7 ddra7 kbie7 pta7/kbi7 b 0 ddrb0 pwm pwmcr $0078 pwm0e ptb0/pwm0 1 ddrb1 pwm1e ptb1/pwm1 2 ddrb2 pwm2e ptb2/pwm2 3 ddrb3 pwm3e ptb3/pwm3 4 ddrb4 pwm4e ptb4/pwm4 5 ddrb5 pwm5e ptb5/pwm5 6 ddrb6 pwm6e ptb6/pwm6 7 ddrb7 pwm7e ptb7/pwm7 c 0 ddrc0 adc adscr $003b adch[4:0] ptc0/adc0 1 ddrc1 ptc1/adc1 2 ddrc2 ptc2/adc2 3 ddrc3 ptc3/adc3 4 ddrc4 ptc4/adc4 5 ddrc5 ptc5/adc5 6 ddrc6 ? ? ? ptc6 d 0 ddrd0 sync pdcr $0069 dclke ptd0/dclk 1 ddrd1 dee ptd1/de 2 ddrd2 voute ptd2/vout 3 ddrd3 houte ptd3/hout 4 ddrd4 ddc12ab ddcscle ptd4/ddcscl 5 ddrd5 ddcdate ptd5/ddcsda 6 ddrd6 mmiic iicscle ptd6/iicscl 7 ddrd7 iicdate ptd7/iicsda e 0 ddre0 usb pecr $0068 usbds1e pte0/dplus1 1 ddre1 pte1/dminus1 2 ddre2 usbds2e pte2/dplus2 3 ddre3 pte3/dminus2 4 ddre4 usbds3e pte4/dplus3 5 ddre5 pte5/dminus3 6 ddre6 usbds4e pte6/dplus4 7 ddre7 pte7/dminus4 input/output (i/o) ports port a mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 297 19.3 port a port a is an 8-bit special- function port that shares all eight of its pins with the keyboard interrupt module (kbi). (see section 21. keyboard interrupt module (kbi) .) 19.3.1 port a data register the port a data register (p ta) contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. kbi[7:0] ? keyboard interrupt pins the keyboard interrupt enable bits , kbie[7:0], in the keyboard interrupt enable register (kbier), enable the port a pins as external interrupt pins. (see 19.3.3 port a options and section 21. keyboard interrupt module (kbi) .) address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: kbi7 kbi6 kbi5 kbi4 kbi3 kbi2 kbi1 kbi0 figure 19-2. port a data register (pta) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 298 input/output (i/o) ports freescale semiconductor 19.3.2 data dir ection register a data direction register a (ddra) dete rmines whether each port a pin is an input or an output. wr iting a logic 1 to a d dra bit enables the output buffer for the corresponding port a pi n; a logic 0 dis ables the output buffer. ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 19-4 shows the port a i/o logic. figure 19-4. port a i/o circuit address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 19-3. data dir ection register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus input/output (i/o) ports port a mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 299 when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 19-2 summarizes the operation of the port a pins. 19.3.3 port a options the keyboard interrupt enabl e register (kbier) se lects the port a pins for keyboard interrupt function or as standar d i/o function. (see section 21. keyboard interr upt module (kbi) .) kbie[7:0] ? keyboard interrupt enable bits setting a kbiex bit to logic 1 c onfigures the pt ax/kbix pin for keyboard interrupt function. reset clears the kbiex bits. 1 = ptax/kbix pin configur ed as kbix interrupt pin 0 = ptax/kbix pin configured as pt ax standard i/o pin table 19-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] address: $004f bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 19-5. keyboard interr upt enable register (kier) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 300 input/output (i/o) ports freescale semiconductor 19.4 port b port b is an 8-bit special- function port that shares all eight of its pins with the pulse width modulator (pwm). (see section 12. pulse width modulator (pwm) .) 19.4.1 port b data register the port b data register (p tb) contains a data latch for each of the eight port pins. ptb[7:0] ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. pwm[7:0] ? pwm outputs pins the pwm output enable bits pwm7e? pwm0e, in the pwm control register (pwmcr) enable port b pins as pwm output pins. (see 19.4.3 port b options and section 12. pulse width modulator (pwm) .) address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: pwm7 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 figure 19-6. port b data register (ptb) input/output (i/o) ports port b mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 301 19.4.2 data dir ection register b data direction register b (ddrb) dete rmines whether each port b pin is an input or an output. wr iting a logic 1 to a d drb bit enables the output buffer for the corresponding port b pi n; a logic 0 dis ables the output buffer. ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. figure 19-8 shows the port b i/o logic. figure 19-8. port b i/o circuit address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 19-7. data direct ion register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 302 input/output (i/o) ports freescale semiconductor when bit ddrbx is a l ogic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 19-3 summarizes the operation of the port b pins. 19.4.3 port b options the pwm control register (pwmcr) selects the port b pins for pwm function or as standard i/o function. (see section 12. pulse width modulator (pwm) .) pwm7e?pwm0e ? pwm output enable bits setting a pwmxe bit to logic 1 configures th e ptbx/pwmx pin for pwm output function. rese t clears the pwmxe bits. 1 = ptbx/pwmx pin configured as pwmx interrupt pin 0 = ptbx/pwmx pin configured as ptbx standard i/o pin table 19-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] address: $0078 bit 7654321bit 0 read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 figure 19-9. pwm cont rol register (pwmcr) input/output (i/o) ports port c mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 303 19.5 port c port c is an 7-bit specia l-function port that shares six of its pins with the analog-to-digital converte r (adc) module. (see section 13. analog-to- digital converter (adc) .) 19.5.1 port c data register the port c data register (ptc) contains a data latch for each of the seven port c pins. ptc[6:0] ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. adc[5:0] ? analog-to -digital input pins adc[5:0] are pins used for the i nput channels to the analog-to-digital converter module. the channel se lect bits, adch[4:0], in the adc status and control register define which port c pin will be used as an adc input and overrides any control from t he port i/o logic. (see 19.5.3 port c options and section 13. analog-to-digital converter (adc) .) address: $0002 bit 7654321bit 0 read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative function: adc5 adc4 adc3 adc2 adc1 adc0 = unimplemented figure 19-10. port c da ta register (ptc) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 304 input/output (i/o) ports freescale semiconductor note: care must be taken w hen reading port c while applying analog voltages to adc5?adc0 pins . if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptcx/adcx pin, while ptc is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. 19.5.2 data dir ection register c data direction register c (ddrc) determines whet her each port c pin is an input or an output. writ ing a logic 1 to a dd rc bit enables the output buffer for the corresponding port c pi n; a logic 0 dis ables the output buffer. ddrc[6:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[6:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 19-12 shows the port c i/o logic. address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 19-11. data direct ion register c (ddrc) input/output (i/o) ports port c mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 305 figure 19-12. port c i/o circuit when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 19-4 summarizes the operation of the port c pins. 19.5.3 port c options the adch[4:0] bits in the adc status and control register defines which ptcx/adcx pin is used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. (see section 13. analog-to- digital converter (adc) .) table 19-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrc[6:0] pin ptc[6:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddrc[6:0] ptc[6:0] ptc[6:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 306 input/output (i/o) ports freescale semiconductor 19.6 port d port d is an 8-bit special-function port t hat shares two of its pins with the multi-master iic (mmiic ) module, two of its pins with the ddc12ab module, and four of its pins with the sync processor. 19.6.1 port d data register the port d data register (ptd) contains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software-p rogrammable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. iicsda, iicscl ? multi-mast er iic data and clock pins the ptd7/iicsda and ptd6/iicscl pi ns are multi-master iic data and clock pins. when the iicdate and iicscle bits in the port d control register (pdcr) ar e clear, the pt d7/iicsda and ptd6/iicscl pins are avail able for general-purpose i/o. (see 19.6.3 port d options .) ddcscl, ddcsda ? ddc12ab data and clock pins the ptd4/ddcscl and ptd5/ddcsda pins are ddc12ab clock and data pins respectively. when the ddcscle and ddcdate bits in the port d control register (pdcr) are clear, the ptd4/ddcscl and ptd5/ddcsda pins are available for general-purpose i/o. (see 19.6.3 port d options .) address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative function: iicsda iicsc l ddcsda ddcscl hout vout de dclk figure 19-13. port d da ta register (ptd) input/output (i/o) ports port d mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 307 hout? sync processor hout pulse output pin the ptd3/hout pin is t he sync processor hout pulse output pin. when the houte bit in the port d control register (pdcr) is clear, the ptd3/hout pin is available for general-purpo se i/o. (see 19.6.3 port d options .) vout ? sync processor vout pulse output pin the ptd2/vout pin is t he sync processor vout pulse output pin. when the voute bit in the port d cont rol register (pdcr) is clear, the ptd2/vout pin is available for general-purpos e i/o. (see 19.6.3 port d options .) de ? sync processor de pulse output pin the ptd1/de pin is the sync processo r de pulse output pin. when the dee bit in the port d control register (pdcr) is clear, the ptd1/de pin is available fo r general-purpose i/o. (see 19.6.3 port d options .) dclk ? sync processor dclk pulse output pin the ptd0/dclk pin is the sync proc essor dclk pulse output pin. when the dclke bit in the port d con trol register (pdcr) is clear, the ptd0/dclk pin is available for general-purpose i/o. (see 19.6.3 port d options .) 19.6.2 data dir ection register d data direction register d (ddrd) determines whet her each port d pin is an input or an output. writ ing a logic 1 to a dd rd bit enables the output buffer for the corresponding port d pi n; a logic 0 dis ables the output buffer. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 19-14. data direct ion register d (ddrd) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 308 input/output (i/o) ports freescale semiconductor ddrd[7:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction regist er d bits fr om 0 to 1. figure 19-15 shows the port d i/o logic. figure 19-15. port d i/o circuit when bit ddrdx is a l ogic 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 19-5 summarizes the operation of the port d pins. table 19-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus input/output (i/o) ports port d mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 309 19.6.3 port d options the port d control register (pdcr) selects the po rt d pins for module function or as st andard i/o function. iicdate ? mmiic data pin enable this bit is set to conf igure the ptd7/iicsda pi n for iicsda function. reset clears this bit. 1 = ptd7/iicsda pin conf igured as iicsda pin 0 = ptd7/iicsda pin conf igured as standard i/o pin iicscle ? mmiic clock pin enable this bit is set to conf igure the ptd6/iicscl pi n for iicscl function. reset clears this bit. 1 = ptd6/iicscl pin conf igured as iicscl pin 0 = ptd6/iicscl pin conf igured as standard i/o pin ddcdate ? ddc data pin enable this bit is set to configure the ptd5/ ddcsda pin for ddcsda function. reset clears this bit. 1 = ptd5/ddcsda pin conf igured as ddcsda pin 0 = ptd5/ddcsda pin configur ed as standard i/o port ddcscle ? ddc clock pin enable this bit is set to c onfigure the ptd4/ddc scl pin for ddcscl function. reset clears this bit. 1 = ptd4/ddcscl pin configured as ddcscl pin 0 = ptd4/ddcscl pin confi gured as standard i/o port address: $0069 bit 7654321bit 0 read: iicdate iicscle ddcdate ddcscle houte voute dee dclke write: reset:00000000 figure 19-16. port d co ntrol register (pdcr) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 310 input/output (i/o) ports freescale semiconductor houte ? hout pin enable this bit is set to c onfigure the ptd3/hout pin for sync processor hout output. reset clears this bit. 1 = ptd3/hout pin conf igured as hout pin 0 = ptd3/hout pin confi gured as standard i/o pin voute ? vout pin enable this bit is set to c onfigure the ptd2/vout pin for sync processor vout output. reset clears this bit. 1 = ptd2/vout pin conf igured as vout pin 0 = ptd2/vout pin confi gured as standard i/o pin dee ? de pin enable this bit is set to conf igure the ptd1/de pin for sync processor de output. reset clears this bit. 1 = ptd1/de pin configured as de pin 0 = ptd1/de pin configur ed as standard i/o pin dclke ? dclk pin enable this bit is set to c onfigure the ptd0/dclk pin for sync processor dclk output. reset clears this bit. 1 = ptd0/dclk pin conf igured as dclk pin 0 = ptd0/dclk pin configur ed as standard i/o pin input/output (i/o) ports port e mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 311 19.7 port e port e is an 8-bit special- function port that shares all of its pins with the universal serial bus module. (see section 14. univer sal serial bus module (usb) .) 19.7.1 port e data register the port e data register (p te) contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits these read/write bits are software-p rogrammable. data direction of each port e pin is under the control of the corresponding bit in data direction register e. reset has no effect on port e data. dplusx and dminusx ? downstream pairs of usb hub data pins the dplusx and dminusx pins ar e the data pin pairs of the universal serial bus hu b. when the usbdsxe bit in the port e control register (pecr) is clear, t he corresponding pte/dplusx and pte/dminusx pins are availabl e for general-purpose i/o. (see 19.7.3 port e options .). address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: dminus4 dplus4 dminus3 dplus3 dminus2 dplus2 dminus1 dplus1 figure 19-17. port e da ta register (pte) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 312 input/output (i/o) ports freescale semiconductor 19.7.2 data dir ection register e data direction register e (ddre) dete rmines whether each port e pin is an input or an output. wr iting a logic 1 to a d dre bit enables the output buffer for the corresponding port e pi n; a logic 0 dis ables the output buffer. ddre[7:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. figure 19-19 shows the port e i/o logic. figure 19-19. port e i/o circuit address: $0009 bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 19-18. data direct ion register e (ddre) read ddre ($0009) write ddre ($0009) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus input/output (i/o) ports port e mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor input/output (i/o) ports 313 when bit ddrex is a l ogic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 19-6 summarizes the operation of the port e pins. 19.7.3 port e options the port e control regi ster (pecr) selects the port e pins for usb module function or as standard i/o function. usbds4e?usbds1e ? usb hub data pins enable setting a usbdsxe bit to logic 1 configures the corresponding pte/dplusx and pte/dminusx pins for usb hub downstream port function. re set clears the usbdsxe bits. 1 = pte/dplusx and pte/dminusx pins configured as usb pins 0 = pte/dplusx and pte/dminusx pins configured as standard i/o pins table 19-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to ptd read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddre[7:0] pin pte[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddre[7:0] pte[7:0] pte[7:0] address: $0068 bit 7654321bit 0 read: r usbds4e usbds3e usbds2e usbds1e write: reset: 0000 = unimplemented figure 19-20. port e c ontrol register (pecr) input/output (i/o) ports data sheet mc68hc908ld64 ? rev. 3.0 314 input/output (i/o) ports freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor external interrupt (irq) 315 data sheet ? mc68hc908ld64 section 20. external interrupt (irq) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 20.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.5 irq status and contro l register (intscr) . . . . . . . . . . . . . . 319 20.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 320 20.2 introduction the irq (external interrupt) module pr ovides a maskable interrupt input. 20.3 features features of the irq modul e include the following: a dedicated external interrupt pin, irq irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pull-up resistor external interrupt (irq) data sheet mc68hc908ld64 ? rev. 3.0 316 external interrupt (irq) freescale semiconductor 20.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 20-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clea r the interrupt latch by writing to the acknowledge bit in the inte rrupt status and control register (intscr). writing a logic 1 to th e ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falli ng-edge or falling-edge and low-level- triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-trigger ed only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the cpu interrupt request remains set unt il both of the following occur: vector fetch or software clear return of the interr upt pin to logic 1 the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear the la tch and the mode control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bit in the intscr mask a ll external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. external interrupt (irq) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor external interrupt (irq) 317 note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including ex ternal interrupt requests. (see 9.6 exception control .) figure 20-1. irq module block diagram addr.register name bit 7654321bit 0 $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 20-2. irq i/o register summary ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pull - up device irq external interrupt (irq) data sheet mc68hc908ld64 ? rev. 3.0 318 external interrupt (irq) freescale semiconductor 20.4.1 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falling- edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the interrupt stat us and control register (intscr). the ack bit is useful in appl ications that poll the irq pin and require software to clear the irq la tch. writing to the ack bit prior to leaving an interrupt service r outine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bi t latches another interrupt request. if t he irq mask bit, imask, is clear, the cpu loads the progr am counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software cl ear and the retu rn of the irq pin to logic 1 may occur in any order. the interrupt request rema ins pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby cl earing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. use the bih or bil in struction to read the logic level on the irq pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. external interrupt (irq) irq status and control register (intscr) mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor external interrupt (irq) 319 20.5 irq status and co ntrol register (intscr) the irq status and control register (intscr) controls and monitors operation of the irq m odule. the intscr has t he following functions: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering se nsitivity of the irq interrupt pin irqf ? irq flag this read-only status bi t is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interr upt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/lev el select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt reques ts on falling edges only address: $001e bit 7654321bit 0 read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 20-3. irq status and control register (intscr) external interrupt (irq) data sheet mc68hc908ld64 ? rev. 3.0 320 external interrupt (irq) freescale semiconductor 20.6 irq module du ring break interrupts the system integration module (sim) co ntrols whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 9. system in tegration module (sim) .) to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writi ng to the ack bit in the irq status and control regi ster during the break state has no effect on the irq latch. mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 321 data sheet ? mc68hc908ld64 section 21. keyboard interrupt module (kbi) 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 21.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 21.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 21.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 21.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 326 21.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 327 21.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 21.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 328 21.2 introduction the keyboard interrupt module (kbi ) provides eight independently maskable external interrupts whic h are accessible via pta0?pta7. when a port pin is enabled for keyboard interr upt function, an internal pull-up device is also enabled on the pin. keyboard interrupt module (kbi) data sheet mc68hc908ld64 ? rev. 3.0 322 keyboard interrupt module (kbi) freescale semiconductor 21.3 features features of the keyboard inte rrupt module (kbi) include: eight keyboard interrupt pins with pull-up devices separate keyboard in terrupt enable bits and one keyboard interrupt mask programmable edge-only or edge- and level- interrupt sensitivity exit from low-lower modes 21.4 i/o pins the eight keyboard interrupt pins are shar ed with standard port i/o pins. the full name of the kbi pins are listed in table 21-1 . the generic pin name appear in the te xt that follows. addr.register name bit 7654321bit 0 $004e keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $004f keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 21-1. kbi i/o register summary table 21-1. pin name conventions kbi generic pin name full mcu pin name pin selected for kbi function by kbiex bit in kbier kbi0?kbi7 pta0/kbi0?pta7/kbi7 kbie0?kbie7 keyboard interrupt module (kbi) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 323 21.5 functional description figure 21-2. keyboard inte rrupt module block diagram writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin al so enables its internal pull-up device. a logi c 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: kbie0 kbie7 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi7 kbi0 synchronizer keyf keyboard interrupt request to pull-up enable to pull-up enable keyboard interrupt module (kbi) data sheet mc68hc908ld64 ? rev. 3.0 324 keyboard interrupt module (kbi) freescale semiconductor vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackk bit in the keyboa rd status and control register (kbscr). the a ckk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask k, is clear, the cpu loads the program counter with the vector address at locations $ffe2 and $ffe3. return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the key board interrupt pin is falling-edge- sensitive only. with mo dek clear, a vector fetc h or software clear immediately clears the ke yboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the ke yboard status and control register can be used to see if a pending inte rrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications wh ere polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an inpu t, overriding t he data direction register. however, the dat a direction register bi t must be a logic 0 for software to read the pin. keyboard interrupt module (kbi) keyboard initialization mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 325 21.6 keyboard initialization when a keyboard interrupt pin is enabl ed, it takes time for the pull-up device to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoi d a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in data di rection register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 21.7 i/o registers these registers control a nd monitor operation of the keyboard module: keyboard status and cont rol register (kbscr) keyboard interrupt enabl e register (kbier) keyboard interrupt module (kbi) data sheet mc68hc908ld64 ? rev. 3.0 326 keyboard interrupt module (kbi) freescale semiconductor 21.7.1 keyboard stat us and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity keyf ? keyboard flag bit this read-only bit is set when a ke yboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. rese t clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from gene rating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard tri ggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $004e bit 7654321bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 21-3. keyboard status and control regi ster (kbscr) keyboard interrupt module (kbi) low-power modes mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor keyboard interrupt module (kbi) 327 21.7.2 keyboard inte rrupt enable register the keyboard interrupt enabl e register enables or disables each port a pin to operate as a ke yboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax/kbix pin enabled as keyboard interrupt pin 0 = ptax/kbix pin not enabled as keyboa rd interrupt pin 21.8 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 21.8.1 wait mode the keyboard interrupt module remains ac tive in wait m ode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to brin g the mcu out of wait mode. 21.8.2 stop mode the keyboard interrupt module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to br ing the mcu out of stop mode. address: $004f bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 21-4. keyboard interr upt enable register (kbier) keyboard interrupt module (kbi) data sheet mc68hc908ld64 ? rev. 3.0 328 keyboard interrupt module (kbi) freescale semiconductor 21.9 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during t he break state. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break stat e has no effect. (see 21.7.1 keyboard status and control register .) mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor computer operating properly (cop) 329 data sheet ? mc68hc908ld64 section 22. computer operating properly (cop) 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 22.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 22.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 22.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 22.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 22.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 332 22.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 22.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 22.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 22.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 22.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 334 22.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register. computer operating properly (cop) data sheet mc68hc908ld64 ? rev. 3.0 330 computer operating properly (cop) freescale semiconductor 22.3 functional description figure 22-1 shows the structure of the cop module. figure 22-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 oscxclk cycles, depending on the state of the co p rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 oscxclk cycle overflow option, a 24 mhz crystal gives a co p timeout period of 10.922ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by cleari ng the cop count er and stages 12 through 5 of the prescaler. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. copctl write oscxclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config) cop rate sel (coprs from config) clear stages 5?12 computer operating properly (cop) i/o signals mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor computer operating properly (cop) 331 a cop reset pulls the rst pin low for 32 oscxcl k cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst . during the br eak state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 22.4 i/o signals the following paragraphs descri be the signals shown in figure 22-1 . 22.4.1 oscxclk oscxclk is the crystal oscillator output signal . oscxclk frequency is equal to the crystal frequency. 22.4.2 stop instruction the stop instruction cl ears the cop prescaler. 22.4.3 copctl write writing any value to the cop c ontrol register (copctl) (see 22.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the prescaler. reading the cop cont rol register retu rns the low byte of the reset vector. 22.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 oscxclk cycles after power-up. computer operating properly (cop) data sheet mc68hc908ld64 ? rev. 3.0 332 computer operating properly (cop) freescale semiconductor 22.4.5 internal reset an internal reset clears the co p prescaler and the cop counter. 22.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 22.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the config register. (see figure 22-2 .) 22.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the config register. (see figure 22-2 .) coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop timeout period is 2 13 ? 2 4 oscxclk cycles 0 = cop timeout period is 2 18 ? 2 4 oscxclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: 0000 ssrec coprs stop copd write: reset:00000000 = unimplemented figure 22-2. configurat ion register (config) computer operating properly (cop) cop control register mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor computer operating properly (cop) 333 22.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 22.6 interrupts the cop does not generate cpu interrupt requests. 22.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is enter ed by having blank rese t vectors and not having v tst on the irq pin, the cop is automatic ally disabled until a por occurs. 22.8 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 22-3. cop cont rol register (copctl) computer operating properly (cop) data sheet mc68hc908ld64 ? rev. 3.0 334 computer operating properly (cop) freescale semiconductor 22.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 22.8.2 stop mode stop mode turns off the oscxclk input to the cop and clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. to prevent inadvertently turning off t he cop with a stop instruction, a configuration option is av ailable that disables the stop instruction. when the stop bit in the config uration register has the stop instruction is disabled, execution of a stop in struction results in an illegal opcode reset. 22.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor break module (brk) 335 data sheet ? mc68hc908ld64 section 23. break module (brk) 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 23.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 338 23.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .338 23.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 338 23.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 338 23.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 23.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 23.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 23.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 23.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 339 23.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 342 23.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. break module (brk) data sheet mc68hc908ld64 ? rev. 3.0 336 break module (brk) freescale semiconductor 23.3 features features of the br eak module include: accessible input/output (i/o) regi sters during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 23.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal to the cpu. the cpu then loads the instruct ion register with a software interrupt instruction (swi) afte r completion of the current cpu instruction. the program count er vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 23-1 shows the structure of the break module. break module (brk) functional description mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor break module (brk) 337 figure 23-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 23-2. break modul e i/o register summary break module (brk) data sheet mc68hc908ld64 ? rev. 3.0 338 break module (brk) freescale semiconductor 23.4.1 flag protectio n during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bi ts during the break state. 23.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program count er with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 23.4.3 tim during break interrupts a break interrupt stops the timer counters. 23.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 23.5 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 23.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see section 9. system in tegration module (sim) ). clear the sbsw bit by writi ng logic 0 to it. break module (brk) break module registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor break module (brk) 339 23.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 23.6 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) sim break status register (sbsr) sim break flag con trol register (sbfcr) 23.6.1 break status and control register the break status and control register (brkscr) contai ns break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 23-3. break status an d control register (brkscr) break module (brk) data sheet mc68hc908ld64 ? rev. 3.0 340 break module (brk) freescale semiconductor brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) br eak address match 0 = (when read) no break address match 23.6.2 break addr ess registers the break address register s (brkh and brkl) contai n the high and low bytes of the desired brea kpoint address. reset clears the break address registers. 23.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode a fter exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 23-4. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 23-5. break addr ess register low (brkl) break module (brk) break module registers mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor break module (brk) 341 sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r=reserved figure 23-6. sim break stat us register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. break module (brk) data sheet mc68hc908ld64 ? rev. 3.0 342 break module (brk) freescale semiconductor 23.6.4 sim break flag control register the sim break flag control register (s bfcr) contains a bit that enables software to clear status bits wh ile the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r=reserved figure 23-7. sim break flag c ontrol register (sbfcr) mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor electrical specifications 343 data sheet ? mc68hc908ld64 section 24. electrical specifications 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 24.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 344 24.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 345 24.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 24.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 346 24.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 24.8 timer interface module characterist ics . . . . . . . . . . . . . . . . . 347 24.9 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 24.10 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 348 24.11 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.12 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 349 24.12.1 usb low speed sour ce electrical characte ristics . . . . . . 350 24.12.2 usb high speed source electric al characteristics . . . . . . 351 24.12.3 hub repeater electrical characte ristics . . . . . . . . . . . . . . 352 24.12.4 usb signaling levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 24.13 ddc12ab/mmiic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 24.13.1 ddc12ab/mmiic interface input signal timing . . . . . . . . 354 24.13.2 ddc12ab/mmiic interface output signal timing . . . . . . . 354 24.14 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 355 electrical specifications data sheet mc68hc908ld64 ? rev. 3.0 344 electrical specifications freescale semiconductor 24.2 introduction this section contains electrical and timing specifications. 24.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 24.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd .) table 24-1. absolute maximum ratings characteristic (1) notes : 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +3.9 v input voltage v in v ss ?0.3 to v dd +0.3 v input voltage, +5v pins iicsda, iicscl, ddcsda, dcscl, hsync, vsync, phsync, pvsync, pclk v hin v ss ?0.3 to +5.5 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 80 ma maximum current into v dd i mvdd 80 ma electrical specifications functional operating range mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor electrical specifications 345 24.4 functional operating range 24.5 thermal characteristics table 24-2. operating range characteristic symbol value unit operating temperature range t a 0 to +85 c operating voltage range v dd 3.0 to 3.6 v table 24-3. thermal characteristics characteristic symbol value unit thermal resistance qfp (64 pins) ja 70 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the devi ce. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d (t a + 273 c) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c electrical specifications data sheet mc68hc908ld64 ? rev. 3.0 346 electrical specifications freescale semiconductor 24.6 dc electrical characteristics table 24-4. dc elect rical characteristics characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc , v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?2.0ma) all output pins v oh 2.4 ? ? v output low voltage (i load = 1.6ma) all output pins v ol ??0.4v input high voltage all ports (except ptd4?ptd7), irq , rst , osc1 for +5v rated pins hsync, vsync, phsync, pvsync, pclk, iicsda, iicscl, ddcsda, ddcscl v ih 0.7 v dd 2.0 ? ? v dd 5.5 v input low voltage all ports (except ptd4?ptd7), irq , rst , osc1 for +5v rated pins hsync, vsync, phsync, pvsync, pclk, iicsda, iicscl, ddcsda, ddcscl v il v ss v ss ? ? 0.2 v dd 0.8 v v dd supply current run, usb active, pll on, f op = 6.0 mhz (3) run, usb suspended, pll off, f op = 6.0 mhz (3) wait, usb active, pll on, f op = 6.0 mhz (4) wait, usb suspended, pll off, f op = 6.0 mhz (4) stop (5) 0 c to +85 c 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. cl = 20 pf on osc2. all ports configur ed as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f oscxclk = 24mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; usb in suspend mode, 15k ? 5% termination resistors on d+ and d? pins; all ports configured as inputs; osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with usb in suspend mode, osc1 grounded, 1.5k ? 1% pull-up resistor on d+ pin and 15k ? 1% pull- down resistors on d+ and d? pins, no port pins sourcing current. i dd ? ? ? ? ? 11 9 6 4 100 20 16 12 8 200 ma ma ma ma a i/o ports hi-z leakage current i il ?? 10 a input current all input pins (except below pins) hsync, vsync, phsync, pvsync, pclk i in ? ? ? ? 1 2 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) 6. maximum is highest voltage that por is guaranteed. v por 0?100mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 1.7 ? 6 v pull-up resistor: kbi0?kbi7, rst , irq r pu 30 45 60 k ? low-voltage inhibit, trip falling voltage v tripf 2.45 v low-voltage inhibit, trip rising voltage v tripr 2.6 v low-voltage inhibit reset/recover hysteresis v hys ?150?mv electrical specifications control timing mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor electrical specifications 347 24.7 control timing 24.8 timer interface module characteristics 24.9 oscillator characteristics table 24-5. control timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum freq uency greater than dc for proper operation; see appropriate table for this information. f op ?6mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 50 ? ns table 24-6. tim characteristics characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ? ns table 24-7. oscillat or characteristics characteristic symbol min typ max unit crystal frequency (1) notes : 1. the sync processor module is designed to function at f oscxclk = 24mhz. f oscxclk ?24 ? mhz external clock reference frequency (1), (2) 2. no more than 10% duty cycle deviation from 50% f oscxclk dc 24 ? mhz crystal fixed capacitance (3) c 1 ? 15 ?pf crystal tuning capacitance (3) c 2 ? 15 ?pf feedback bias resistor r b ?2 ? m ? series resistor (3) 3. not required for high frequency crystals r s ?0 ? ? electrical specifications data sheet mc68hc908ld64 ? rev. 3.0 348 electrical specifications freescale semiconductor 24.10 adc electrical characteristics table 24-8. adc elect rical characteristics characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min max unit comments supply voltage v ddad 3.0 3.6 v v dd 10% input voltages v adin 0 v dd v resolution b ad 88bits absolute accuracy a ad 1 2 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v ss v dd v power-up time t adpu 16 t aic cycles conversion time t adc 16 17 t aic cycles sample time (2) 2. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. t ads 5? t aic cycles zero input reading (3) 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. z adi 00 02 hex full-scale reading (3) f adi fd ff hex input capacitance c adi ? 8 pf not tested input leakage (4) port c 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current. ?? 1 a electrical specifications sync processor timing mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor electrical specifications 349 24.11 sync processor timing 24.12 usb dc electrical characteristics table 24-9. sync processor timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit vsync input sync pulse t vi.sp 82048 s hsync input sync pulse t hi.sp 0.1 6 s vsync to vsynco delay (8pf loading) t vvd 30 40 s hsync to hsynco delay (8pf loading) t hhd 30 40 s de set-up time of dclk t desu 4? s de hold time of dclk t dehd 4? s table 24-10. usb dc elec trical characteristics characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol conditions min typ max unit hi-z state data line leakage i lo 0v electrical specifications usb dc electrical characteristics mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor electrical specifications 351 24.12.2 usb high speed source electrical characteristics table 24-12. usb high speed source electri cal characteristics characteristic symbol conditions (1) notes : 1. all voltages measured from local ground, unless otherwise sp ecified. all timings use a capacitive load of 50pf, unless otherwise specified. high speed timings have a 1.5k ? pull-up to 2.8v on the d+ data line. min typ max unit internal operating frequency f op 6mhz transition time (2) rise time fall time 2. transitions are measured fr om 10% to 90% of the data signal. the rising and falling edges should be smoothly transitioning (monotonic). capacitive loading in cludes 50pf of tester capacitance. t r t f c l =50pf c l =50pf 4 4 20 20 ns ns rise/fall time matching t rfm t r /t f 90 110 % output signal crossover voltage v crs 1.3 2.0 v high speed data rate t drate 12mbs 0.25% 11.97 12.03 mbs frame interval t frame 1.0ms 0.05% 0.9995 1.0005 ms source differential driver jitter to next transition for paired transitions t dj1 t dj1 c l =50pf notes (3), (4) 3. timing differences between the differential data signals. 4. measured at crossover point of differential data signals. ?3.5 ?4.0 3.5 4.0 ns ns source eop width teopt note (4) 160 175 ns differential to eop tr ansition skew tdeop note (4) ?2 5 ns receive data jit ter tolerance to next transition for paired transitions t jr1 t jr2 c l =50pf notes (3), (4) ?18.5 ?9 18.5 9 ns ns receiver eop width must reject as eop must accept t eopr1 t eopr2 note (4) 40 82 ns ns electrical specifications data sheet mc68hc908ld64 ? rev. 3.0 352 electrical specifications freescale semiconductor 24.12.3 hub repeater el ectrical characteristics table 24-13. hub repeater electrical characteristics low speed hub electri cal characteristics (root port and downstream ports configured as low speed) characteristic symbol conditions note (1),(2),(3) notes : 1. all voltages measured from lo cal ground, unless otherwise specified. 2. all timings use a capacitive load of (c l ) to ground of 50pf, un less otherwise specified. 3. full speed timings have a 1.5k ? pull-up to 2.8v on the d+ data line. min typ max unit hub differential data delay t lhdd note (4),(5),(6) 4. low speed timings have a 1.5k ? pull-up to 2.8v on the d? data line. 5. timing differences between the differential data signals. 6. measured at crossover point of differential data signals. measured from 10% to 90% of the data signal. the rising and falling edges should be smoothly transiti oning (monotonic). the maximum load specification is the maxi mum effective capacitive load allowed that meets the target hub vbus droop of 330mv. 300 ns hub differential driver jitter (including cable) downstream: to next transition for paired transitions upstream to next transition for paired transitions t ldhj1 t ldhj2 t luhj1 t luhj2 note (4),(5),(6) ?45 ?15 45 45 45 15 45 45 ns ns ns ns data bit width distortion after eop. t eop note (4),(6) ?60 60 ns hub eop delay relative to t hdd t leopd note (4),(6) 0200ns hub eop output width skew t lhesk note (4),(6) ?300 300 ns full speed hub electrical characteristics (root port and downstream ports configured as full speed) characteristic symbol conditions (notes 1,2,3) min typ max unit hub differential data delay (with cable) (without cable) t hdd1 t hdd1 note (3),(5),(6) 70 40 ns ns hub differential driver jitter (including cable) to next transition for paired transitions t hdj1 t hdj2 note (3),(5),(6) ?3 ?1 3 1 ns ns data bit width distortion after sop t sop note (3),(6) ?5 5 ns hub eop delay relative to t hdd t eopd note (3),(6) 015ns hub eop output width skew t hesk note (3),(6) ?15 15 ns electrical specifications usb dc electrical characteristics mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor electrical specifications 353 24.12.4 usb si gnaling levels table 24-14. usb signaling levels bus state signaling levels from originating driver at receiver differential ?1? (d+) ? (d?) > 200 mv and d+ or d? > v se (min.) differential ?0? (d+) ? (d?) < ?200 mv and d+ or d? > v se (min.) data j state: low speed full speed differential ?0? differential ?1? data k state: low speed full speed differential ?1? differential ?0? idle state: low speed full speed differential ?0? and d? > v se (max.) and d+ < v se (min.) differential ?1? and d+ > v se (max.) and d? < v se (min.) resume state: low speed full speed differential ?1? and d+ > v se (max.) and d? < v se (min.) differential ?0? and d? > v se (max.) and d+ < v se (min.) start of packet (sop) data lines switch from idle to k state end of packet (eop) d+ and d? < v se (min) for 2 bit times (1) followed by an idle for 1 bit time notes : 1. the width of eop is defined in bit times relative to the speed of transmission. d+ and d? < v se (min) for 1 bit time (2) followed by a j state 2. the width of eop is defined in bit times relative to the device type receiving the eop. disconnect (upstream only) ? d+ and d? < v se (max) for 2.5 s connect (upstream only) ? d+ or d? > v se (max) for 2.5 s reset (downstream only) d+ and d? < v se for 10 ms d+ and d? < v se (min) for 2.5 s (must be recognized within 5.5 s) (3) 3. these times apply to an active device that is not in the suspend state. electrical specifications data sheet mc68hc908ld64 ? rev. 3.0 354 electrical specifications freescale semiconductor 24.13 ddc12ab/mmiic timing figure 24-1. mmii c signal timings 24.13.1 ddc12ab/mmiic inte rface input signal timing 24.13.2 ddc12ab/mmiic interf ace output signal timing table 24-15. ddc12ab/mmiic interface input signal timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit start condition hold time t hd.sta 2? t cyc clock low period t low 4? t cyc clock high period t high 4? t cyc data set-up time t su.dat 250 ? ns data hold time t hd.dat 0?ns start condition set-up time (for repeated start condition only) t su.sta 2? t cyc stop condition set-up time t su.sto 2? t cyc table 24-16. ddc12ab/ mmiic interface ou tput signal timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit sda/scl rise time (2) 2. with 200pf loading on the sda/scl pins. t r ?1 s sda/scl fall time t f ? 300 ns data set-up time t su.dat t low ?ns data hold time t hd.dat 0?ns sda scl t hd.sta t low t high t su.dat t hd.dat t su.sta t su.sto electrical specifications flash memory characteristics mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor electrical specifications 355 24.14 flash memory characteristics table 24-17. flash memory electrical characteristics characteristic symbol min max unit program bus clock frequency ? 1 ? mhz flash block size $0c00?$0fff $1000?f9ff ? ? 128 512 bytes bytes flash programming size ? 64 bytes read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32k 6m hz page erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 10 ? ms mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, bu t it reduces the endurance of the flash memory. 10 ? ms pgm/erase to hven set up time t nvs 5? s high-voltage hold time t nvh 5? s high-voltage hold time (mass erase) t nvhl 100 ? s program hold time t pgs 20 ? ns program time t prog 20 40 s return to read time t rcv (4) 4. t rcv is defined as the time it n eeds before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1? s cumulative program hv period 4,7616 bytes array 13k-bytes array t hv (5) t hv1 (6) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 64) t hv max. 6. t hv1 is the t hv spec for 13k-bytes array ? ? 6 3 ms ms row erase endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles row program endurance (8) 8. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles data retention time (9) 9. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ?10?years electrical specifications data sheet mc68hc908ld64 ? rev. 3.0 356 electrical specifications freescale semiconductor mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor mechanical specifications 357 data sheet ? mc68hc908ld64 section 25. mechanical specifications 25.1 contents 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 25.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 358 25.2 introduction this section gives t he dimensions for: 64-pin plastic quad flat pack (case #840b) mechanical specifications data sheet mc68hc908ld64 ? rev. 3.0 358 mechanical specifications freescale semiconductor 25.3 64-pin plastic quad flat pack (qfp) figure 25-1. 64-pin qfp (case #840b) l l ?a? ?b? detail a ?d? b a s v detail a p b b d ?a?, ?b?, ?d? c ?c? e h g m m detailc seating plane datum plane 1 16 ?h? 0.01 (0.004) r detail c datum plane ?h? t u q k w x s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s h 48 33 s a?b m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ? 0.25 ? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 ? 0.005 ? u 0 ?0 ? v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b?b mc68hc908ld64 ? rev. 3.0 data sheet freescale semiconductor ordering information 359 data sheet ? mc68hc908ld64 section 26. ordering information 26.1 contents 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 26.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 26.2 introduction this section contains ordering numbers for the mc68hc908ld64. 26.3 mc order numbers table 26-1. mc order numbers mc order number (1) notes : 1. i = operating temperature range: 0 c to +85 c fu = quad flat pack package operating temperature range MC68HC908LD64IFU 64-pin qfp 0 c to +85 c ordering information data sheet mc68hc908ld64 ? rev. 3.0 360 ordering information freescale semiconductor how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor hong kong ltd. 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: www.freescale.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004 mc68hc908ld64 rev. 3 07/2004 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semico nductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s tech nical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shal l indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. learn more : for more information about freescale products, please visit www.freescale.com |
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